Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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Apr 1, 2022
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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E012 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop & Mobile H&HXMobile U OnlyMobile H
Process NodeIntel 4TSMC N3BTSMC N3BIntel 18A
DateQ4 2023Desktop-Q4-2024
H&HX-Q1-2025
Q4 2024Q1 2026 ?
Full Die6P + 8P8P + 16E4P + 4E4P + 8E
LLC24 MB36 MB ?12 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15



Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)



 

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MS_AT

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Jul 15, 2024
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We have reports that disabling VBS improves memory latency, people expect we'll see big swings in performance from one review to another, based on wheter security features are (properly) disabled or left enabled to emulate the casual user experience.
By reports do you mean people have confirmed in the past that VBS makes the mem latency worse, or do you mean this one guy who got Arrow Lake ahead of release?
 

Joe NYC

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Jun 26, 2021
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Hmmm. Last time I checked, tiles are chiplets. Also, I thought Zen 6 was using silicon bridges, not an interposer?

According to some rumors, it will more likely use the same fanout packaging as Navi31 / 32. Which may also be used in Strix Halo.

We will see if Strix Halo achieves some improvement in latency vs. desktop Zen 5. Except, using LPDDR5, which has higher latency, is going to make it more difficult to get apples to apples comparison.

But, the fanout packaging should have similar latency as Foveros in Arrow Lake.
 

coercitiv

Diamond Member
Jan 24, 2014
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By reports do you mean people have confirmed in the past that VBS makes the mem latency worse, or do you mean this one guy who got Arrow Lake ahead of release?
I meant the one guy, obviously nothing is certain until we get the first wave of reviews out, and it's not worth investigating if the report is real when more trustworthy data is just around the corner.
 

Hulk

Diamond Member
Oct 9, 1999
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As for review quality, I would much prefer quality of quantity.
For example, instead of 35 benchmarks that include no specifications as to how they were performed and operating parameters, provide 10 or 12 fully documented benches showing at least average power during the benchmark run and average frequency during the run. Other details like Vcore would be nice as well. Also please include all important bios settings used for testing.

Unfortunately we generally only get those types of benches when WE perform them and report back here.
 
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cebri1

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Jun 13, 2019
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As for review quality, I would much prefer quality of quantity.
For example, instead of 35 benchmarks that include no specifications as to how they were performed and operating parameters, provide 10 or 12 fully documented benches showing at least average power during the benchmark run and average frequency during the run. Other details like Vcore would be nice as well. Also please include all important bios settings used for testing.

Unfortunately we generally only get those types of benches when WE perform them and report back here.
Phoronix is the one to look for.
 
Jul 27, 2020
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Remind me again, please? What was the final concenus regarding Lunar Lake? Total fail? Amazing? Good battery life/ST performance, not so good MT performance? Where Intel's performance/efficiency claims substantiated by reviews?

I just want to know where we are before we dive into ARL.
My takeaway from reading the reviews is that it's way more preferable to MTL-H. Can't wait to see 258V laptops at least get to the $500 mark (they usually do for certain brands like Lenovo and sometimes even HP). But right now, they seem to be priced $150 more than Ryzen AI laptops which are themselves overpriced to begin with.
 

Hitman928

Diamond Member
Apr 15, 2012
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Not entirely. Tiles are not like AMD chiplets. Conversely, AMD chiplets can't be called Tiles either.

Tiles are an advanced from of chiplet design compared to older chiplet design AMD uses. AMD chiplets are hardwired on substrate. Intel Tiles sit on interposer that sits on top of substrate.

AMD is expected to switch to Intel's advanced Tile like chiplet configuration with Zen 6.

You could call AMD's approach tiles and Intel's approach chiplets, there's no technical distinction that causes the different naming. AMD was first and called its approach chiplets. Intel followed and didn't want to be seen as copying AMD, so they called their approach tiles, that's it.
 

Josh128

Senior member
Oct 14, 2022
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As for review quality, I would much prefer quality of quantity.
For example, instead of 35 benchmarks that include no specifications as to how they were performed and operating parameters, provide 10 or 12 fully documented benches showing at least average power during the benchmark run and average frequency during the run. Other details like Vcore would be nice as well. Also please include all important bios settings used for testing.

Unfortunately we generally only get those types of benches when WE perform them and report back here.
Watch out for David Huangs and Chips N Cheese's articles. Those are the most technical reviewers on the net.
 

dullard

Elite Member
May 21, 2001
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You could call AMD's approach tiles and Intel's approach chiplets, there's no technical distinction that causes the different naming. AMD was first and called its approach chiplets. Intel followed and didn't want to be seen as copying AMD, so they called their approach tiles, that's it.
Again with this. Intel was first (Pentium D), AMD and the internet called intel's Pentium D chips glued together. Years later AMD comes out with chiplets\tiles and Intel jokes back that they are glued together referring back to AMD's swipe at Intel. Suddenly everyone in all forums says AMD was first with chiplets\tiles. AMD was first with a good implementation. But that doesn't make AMD first.
 
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cebri1

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Jun 13, 2019
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The game power consumption of Ultra 9 285K is significantly reduced compared with the previous generation. The average power consumption of the 7 games is only 76W, which is less than half of the i9-14900KS, and even lower than the 8-core Ryzen 7 9700X
At least power consumption is now at reasonable levels.
 

Hitman928

Diamond Member
Apr 15, 2012
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Again with this. Intel was first (Pentium D), AMD called intel's Pentium D chips glued together. Years later AMD comes out with tiles and Intel jokes back that they are glued together referring back to AMD's swipe at Intel. Suddenly everyone in all forums says AMD was first with tiles. AMD was first with a good implementation. But that doesn't make AMD first.

Pentium D and chiplets are actually technically distinct though. Pentium D put 2 full dies on a package and connected them through FSB. Chiplets actually break up the die into incomplete dies that all work together to give full functionality. It’s not the same thing.
 

gdansk

Diamond Member
Feb 8, 2011
3,276
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Again with this. Intel was first (Pentium D), AMD and the internet called intel's Pentium D chips glued together. Years later AMD comes out with tiles and Intel jokes back that they are glued together referring back to AMD's swipe at Intel. Suddenly everyone in all forums says AMD was first with tiles. AMD was first with a good implementation. But that doesn't make AMD first.
Disagree. Pentium D was a different approach. Two of the same chip, either of which was viable alone. AMD disaggregated cores from SoC hence chiplet as either chip is rather useless by itself. And MTL/ARL are like the AMD approach, not the Pentium D approach.
 

Timorous

Golden Member
Oct 27, 2008
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Again with this. Intel was first (Pentium D), AMD and the internet called intel's Pentium D chips glued together. Years later AMD comes out with tiles and Intel jokes back that they are glued together referring back to AMD's swipe at Intel. Suddenly everyone in all forums says AMD was first with tiles. AMD was first with a good implementation. But that doesn't make AMD first.

Intel also had the IO die 1st with Clarkdale.
 

Timorous

Golden Member
Oct 27, 2008
1,775
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Disagree. Pentium D was a different approach. Two of the same chip, either of which was viable alone. AMD disaggregated cores from SoC hence chiplet as either chip is rather useless by itself. And MTL/ARL are like the AMD approach, not the Pentium D approach.

Pretty sure Pentium D was still using a northbridge and FSB. In fact if I recall correctly for core 1 to speak to core 2 it had to go out to the northbridge over the FSB and back again.

Fundamentally the difference between Pentium D and Zen 2 is that instead of having the northbridge on the motherboard the northbridge is on the CPU package.

You could easily call Pentium D the 1st multi CCD design.
 

cebri1

Senior member
Jun 13, 2019
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So pretty OK MT results, latency killing latency sensitive apps. We’ll see if with some fine tuning you can get more acceptable results. Pretty impressive gains in performance per watt.

 

Kepler_L2

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Sep 6, 2020
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