Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

DavidC1 · Oct 24, 2024

gdansk said:
This summarizes x64 desktop in 2024.

Maybe the disappointment with both Zen 5 and Arrowlake is due to unwarranted hype.

How many believed the 30-40% per clock gains by MLID? If people here didn't believe MLID, many outside this forum definitely did.

Zen 5 was hyped because there seemed to be structures that enlarged enough that such high numbers for gains seemed reasonable. It is a lesson that high level disclosures are not worth much.

gdansk · Oct 24, 2024

DavidC1 said:
Maybe the disappointment with both Zen 5 and Arrowlake is due to unwarranted hype.

How many believed the 30-40% per clock gains by MLID? If people here didn't believe MLID, many outside this forum definitely did.

Zen 5 was hyped because there seemed to be structures that enlarged enough that such high numbers for gains seemed reasonable. It is a lesson that high level disclosures are not worth much.

Not me, I had hype levels much lower than that. I expected Zen 5 to be 5% faster than it is. And I expected Arrow Lake to lose to X3D but not regular Zen 5 in gaming.

I don't think either of those were too hype. It would allow desktop 100W+ x86 to be as fast as a fanless tablet from a lifestyle brand for handling web bloat.

Meteor Late · Oct 24, 2024

DavidC1 said:
Sure it does. Because the design teams are different.

Also Skymont is pretty efficient on Lunarlake.

Much lower frequency, though. If Skymont in Lunar Lake was already less efficient than Lion Cove at the upper part of the performance power curve (Geekerwan), it is only getting worse with a 24% bump (3.7 to 4.6GHz) in E core frequency from 268v to 285K compared to a 14% frequency bump (5 to 5.7GHz) in the P core.

Joe NYC · Oct 24, 2024

adroc_thurston said:
They're bleeding share in laptop and pretty aggressively so.
If you mean LNL, then it's more niche than discrete GPUs. But all tablet chips are.

This is going to be a big question. AMD is churning out notebook designs one after another, at faster pace than Intel, and will have a design for nearly every segment of the market and price range. I don't see the 80%-20% market share in favor of Intel as sustainable.

gdansk · Oct 24, 2024

Can someone expand on which factors may contribute the 9950X and 285K having such similar IPC in 1T when it was shown Zen 5 operates as a 4-wide decode design outside of SMT and Lion Cove is apparently up to 8-wide decode?

Too many mispredictions? There isn't more ILP to exploit? Lion Cove is bottlenecked at execution? Then why does Lion Cove have 8 wide decode?

igor_kavinski · Oct 24, 2024

gdansk said:
Too many mispredictions? There isn't more ILP to exploit? Lion Cove is bottlenecked at execution? Then why does Lion Cove have 8 wide decode?

Gotta wait for CnC.

Saylick · Oct 24, 2024

Joe NYC said:
This is going to be a big question. AMD is churning out notebook designs one after another, at faster pace than Intel, and will have a design for nearly every segment of the market and price range. I don't see the 80%-20% market share in favor of Intel as sustainable.

There just isn't the volume for AMD to grab market share, in my opinion. I won't believe it until I see businesses getting AMD CPUs in their corporate laptops as standard.

gdansk · Oct 24, 2024

igor_kavinski said:
Gotta wait for CnC.

I read this but I'm still now sure how it ends up about the same. It seems to have more cache, bigger buffers, better rename, and in many measurements it looks better. But in real world code and SPEC it ends up within the margin of error.

Lion Cove: Intel’s P-Core Roars

Intel’s mobile CPUs have undergone massive changes over the past couple generations as Intel defends its laptop market against AMD, Qualcomm, and to a lesser extent Apple.

chipsandcheese.com

igor_kavinski · Oct 24, 2024

gdansk said:
I read this but I'm still now sure how it ends up about the same.

Something is very wrong there. The drop off after 4KB test size is sad though it fares much better than Ryzen at 64KB test size.

DavidC1 · Oct 24, 2024

gdansk said:
Too many mispredictions? There isn't more ILP to exploit? Lion Cove is bottlenecked at execution? Then why does Lion Cove have 8 wide decode?

This is difficult to know, because we're talking about high level details. Simply put it could be generalized as imbalanced design and shoddy execution.

There was a post a while ago about Tesla engineers saying 8-wide decode on x86 is impossible. So the illogic of Lion Cove is that it did do that despite a 10% gain. One would think 7-wide would have been more than enough. I think they could have stayed at 6-wide for 10% gains.

Plus general purpose performance is not heavily limited by decode. Having more helps, but that alone is not enough. We stayed 4-wide from Core 2 in 2006 to Skylake in 2016, right? ILP, or instruction level parallelism is lower than 2 in average for lots of code. So even 4-wide is double that.

But obviously there are code that benefits from being wider, and Google mentioned this, and so did Jim Keller. And if you improve elsewhere, than the average will go up, and maybe you'll also have more cases where it can reach peak. This is why some believed back in the 2000s, it was hard to get above original Athlon in performance. Yet here we are.

You can see from David Huang's review that Lion Cove regressed in Branch MKPI by 2% over Golden Cove. But Zen 5 got 10% improvement over Zen 4, with 9% Integer gain right? Skymont's 32% Integer gain was roughly matched by 27% in MKPI improvement.

So Lion Cove's 10% gain should have got it's branch predictor little better too, not worse. Branch predictor is very, very important as less misses mean less flushed pipelines, meaning more performance and less wasted power. And it improves ILP. So Lion Cove is wasting it's resources elsewhere, like the overly big decode for one. Where else is LNC wasting it?

adroc_thurston · Oct 24, 2024

gdansk said:
Then why does Lion Cove have 8 wide decode?

IDC.

gdansk said:
Can someone expand on which factors may contribute the 9950X and 285K having such similar IPC in 1T when it was shown Zen 5 operates as a 4-wide decode design outside of SMT and Lion Cove is apparently up to 8-wide decode?

IDC.

DavidC1 · Oct 24, 2024

Adding on the explanation:

To get 100% gain, you can't rely on one unit. Because if that was the case, then the code itself is not general purpose, and extremely specialized. Such as Matrix Math like Linpack, or Dhrystone. If you want to see whether the execution units are functional, then they are useful, for academic purposes.

For GPUs, you need more shaders, more texture units, and more memory bandwidth. Those are the three big basic ones. Then when you take all games into account, then the split would be 33%/33%/33%. So if you quadruple memory bandwidth, but leave the rest same, instead of getting 33x2 improvement, you run into diminishing returns.

In a balanced code, 2x bandwidth = 33% gains in the above simplified example. So you say, "Oh it's not bottlenecked". But that's incorrect. You are memory bandwidth bound, just not 100% because you are running a balanced, real world game, not a scripted benchmark to stress only memory(That's what 100% means).

CPUs are general purpose. So instead of 3 basic units, now you need 10 basic units, that each need to add to the final by 10% to get 100% combined gain. Now that balance is hard, but it's the basic idea. So if you have a bad team, you might put too much effort into one area, and almost nothing in others. Lion Cove goes through the trouble of having an "impossible" 8-wide x86 decode, but doesn't improve in branch prediction. Can you say "IMBALANCE!"?

poke01 · Oct 24, 2024

adroc_thurston said:
IDC

IDK if this refers to Intel teams or you just don’t care 😝

DavidC1 · Oct 24, 2024

Meteor Late said:
Much lower frequency, though. If Skymont in Lunar Lake was already less efficient than Lion Cove at the upper part of the performance power curve (Geekerwan), it is only getting worse with a 24% bump (3.7 to 4.6GHz) in E core frequency from 268v to 285K compared to a 14% frequency bump (5 to 5.7GHz) in the P core.

So it should not reach 5.7GHz. Revolutionary idea? Perhaps...

Apple, the peak chip clocks at 4.4GHz with a 9-stage pipeline and uses a mere 7W in ST. x86 cores are 14-19 stages and uses more than 30W at 5.7GHz.

Less than 30% difference in clocks, for more than double worst-case pipeline stages and 5x the power use. And in Intel's case, it degrades while doing so. And in Arrowlake it had to sacrifice ring bus clocks because 4.6GHz ring was too crazy for it. And isn't Apple beating the 5.7GHz x86 chips in pure ST performance?

@adroc_thurston UOP cache hit is only little higher? 14 is only on a hit. 80% hit rate is 15 stages, and likely 60-70% is more likely for average scalar Int, which makes it 16, which is a magic number. When it misses, it's 19 stages, because adding a uop cache adds a few stages.

Magic number, because that was the number of stages before uop cache. Nehalem had 16. So one cannot help but think uop cache is there to up the clocks while minimizing the consequence of increased pipeline stages. So the real goal is subtly similar to Netburst - clockspeed focus.

(Hmm, with Intel's own x86 Optimization Manual saying that Gracemont's way of decode makes it possible for wide x86 decode without needing uop cache, I would suggest a Unified Core will NOT have uop cache. I'm also gonna say Hyperthreading is gone for UC)

However, there is MORE to 5.7GHz. Because this isn't pure clock scaling. This is insanity, pushing it using any means necessary. So I would also challenge that if they change the ideology and completely redesign for low-5GHz clocks at maximum, then things like cache latencies or sizes can be enlarged quite a bit more now.

poke01 · Oct 24, 2024

ahh I know why it performs well in CB2024, it’s not cause the P core is awesome, it’s because DRAM bandwidth effects ST by a noticeable margin.

The older Cinebench versions are not dependent on memory for ST scaling.

H433x0n · Oct 24, 2024

poke01 said:
ahh I know why it performs well in CB2024, it’s not cause the P core is awesome, it’s because DRAM bandwidth effects ST by a noticeable margin.

The older Cinebench versions are not dependent on memory for ST scaling.

Anyway to prove that? Otherwise we’ll be dealing with conspiracy theories about Maxon and Intel for the next 2 years.

poke01 · Oct 24, 2024

Zen 5 should score much higher than in CB 2024 if it got an updated IOD.

I bet Zen6 will lead in CB2024 in ST.

adroc_thurston · Oct 24, 2024

poke01 said:
IDK if this refers to Intel teams or you just don’t care 😝

Very much Israel.

poke01 said:
Zen 5 should score much higher than in CB 2024 if it got an updated IOD.

It just so happens you're 2 months away from that.

DavidC1 said:
And isn't Apple beating the 5.7GHz x86 chips in pure ST performance?

They're at 4.5 now and 5 isn't far off.

Hulk · Oct 24, 2024

StinkyPinky said:
The Steve's aren't impressed it seems.

But what a poor year so far for CPU launches.

I think Zen 5 looks pretty darn good and Lunar Lake is definitely an improvement for thin and light. ARL has some issues with some applications but I'm waiting a bit to see how things settle out.

mvprod123 · Oct 24, 2024

DavidC1 said:
And isn't Apple beating the 5.7GHz x86 chips in pure ST performance?

CB 2024 ST:
M3: 144
M4: 174

DavidC1 · Oct 24, 2024

adroc_thurston said:
They're at 4.5 now and 5 isn't far off.

LOL! Further proves my point. The gap is so close now it's time to back off on pipelines, high clock speed focus, so you can have a smaller core, be more power efficient, et cetera, et cetera.

This is a way of saying Netburst without directly saying Netburst. Abandon the 2024 Pentium 4 and go back to lower clocks.

Hulk said:
I think Zen 5 looks pretty darn good and Lunar Lake is definitely an improvement for thin and light. ARL has some issues with some applications but I'm waiting a bit to see how things settle out.

I'd love a Lunarlake efficiency x86 laptop. FHD 11.6 inch screen would get 15 hours on a 50WHr battery and be under 2.3lbs while being a 2-in-1 convertible. It simply is not possible with other platforms.

LightningZ71 · Oct 24, 2024

Back to why there is a performance hit for 8p0e, two things come to mind: first, we may be hitting a floor for available threads. Maybe the programs really do need more threads available. Second, does deactivating or just ignoring the e-core clusters negatively affect the L3 slices that they are adjacent to? Either it effectively is unusable, or, the extra latency to cross the ring bus to the next L3 slice is so bad that it obviates it's usefulness to a great degree?

Abwx · Oct 24, 2024

H433x0n said:
Anyway to prove that? Otherwise we’ll be dealing with conspiracy theories about Maxon and Intel for the next 2 years.

Maxon s historical relation with Intel is documented, so why are you doing like it s a conspiration theory while it s a fact.?.

You know better than Maxon s senior software developper.?

gdansk · Oct 24, 2024

DavidC1 said:
I'd love a Lunarlake efficiency x86 laptop.

I haven't seen any interesting Lunar Lake laptops that can compete with MBA. They're all too expensive in comparison. I guess I'll have to wait for discounts but it seems weird that now Apple is the king of $700-1000 laptops...

Hulk · Oct 24, 2024

This is one of those times when I really wish Anand was still doing this so he could tell me what to think right now.

Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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