Power efficiency still pretty meh even with 3nm and all these "efficiency" cores. Multi threaded performance also not that amazing, basically ties zen 5 average.
People seem to be severely over estimating e-cores. The only thing they seem good for is optimizing the die area for Cinebench r24.
I agree. N3B should have provided fertile ground for better power efficiency than we are seeing. If all AMD did was shrink 9950x down to N3B we would expect much better results than this. In fact, we would expect that the additional transistor budget would have been used in the desktop to much better effect IMO.
The e Cores on Arrow Lake seem pretty good to me (especially without SMT). What exactly do you use as evidence for this statement?
Intel is fine? I wholeheartedly disagree.
Foundry is a big problem. Just last year foundry had a $7B loss. That's why their operating income was only $93M despite them having $54.2B revenue!
This year and next year will be another loss in foundries, who knows how big, I wouldn't be surprised If It was even bigger with all the money paid to TSMC.
People shouldn't forget that the money they pay to TSMC is the money, which should have gone to their foundries.
Check out my post from a different thread.
Link
I believe
@511 mentioned this earlier, but Intel design team has relied WAY too much over the years on the foundry making miracles for them. As the cost of new Lithography processes and machines has grown exponentially, continuing on this strategy is a death sentence. Intel must be able to sell its foundry services to spread the obscene cost of the development to others as TSMC does. They ALSO need to get their design teams aligned with the idea that they must design within the limits of the process generation they will release at and not to expect a 1-2 node advantage over the entire industry for their designs to be competitive.
Intel really needed to keep hyperthreading. It's easy to see why Intel is behind without it.
I agree. Study after study has shown that both the power efficiency and space efficiency of SMT is hugely worth it. I am baffled by this decision as well.
AGREED
Their biggest lie: "We axed HT for single threaded performance"
WHAT single thread performance????
You are literally losing in almost 99% of games!!!!
Like, you don't wanna hear my shrieking screaming voice right now, Intel!
Lion Cove's expanded structures probably only work to the max with HT enabled!
First, I believe that the ring bus implementation is hurting Arrow Lake greatly. I am pretty sure that Intel will figure it out in the next iteration and the Lion Cove follow on core will reap huge benefits from it in ST performance (and everyone's blessed games for the love of God).
Second, I have also heard a lot about Lion Coves architecture being created such that the resources are all kept pretty busy and that as a result, SMT would not provide much of an uplift. If that is correct, then it isn't enough for Intel to just slap on SMT, it would require a pretty big overhaul.
With SMT they would had gained the equivalent of 2P assuming a paltry 25% SMT gain, that s not negligible, eventualy they ll get back to this approach in their next designs as the bigger a core the more the SMT relevance.
Read my reply above. I think it would require an overhaul of the design to make SMT an effective part of the design.
This. AMD is utterly dominating the Cloud and server hosting market. If you need a VPS/VDS or a dedicated server it's all Ryzen9 for frequency or Epyc for compute. SMT allows hosts to cheaply sell more vCPUs per node, and that allows more VM nodes per machine. As cool as Granite Ridge is, it has nothing against Turin dense for the cloud.
... and THIS is one of the biggest problems Intel has. AMD's Zen 5 design works beautifully in DC applications. It is interesting that only Turin dense is on N3E while Turin is on N4P. I will be interested to see how Clearwater Forest on 18A does.
Maybe the disappointment with both Zen 5 and Arrowlake is due to unwarranted hype.
How many believed the 30-40% per clock gains by MLID? If people here didn't believe MLID, many outside this forum definitely did.
Zen 5 was hyped because there seemed to be structures that enlarged enough that such high numbers for gains seemed reasonable. It is a lesson that high level disclosures are not worth much.
Certainly we all love a good ole Core 2 release like back in the day. Better in everything by a long shot, less power ..... and by God, it is even a nicer looking processor!
I think that with the death of "Tock" due to the exponential cost of new process nodes ..... and .... you know ... physics, we will be seeing more "Tick's" in the future and that 5% to 10% is about all we should be expecting IMHO.
......
So Lion Cove's 10% gain should have got it's branch predictor little better too, not worse. Branch predictor is very, very important as less misses mean less flushed pipelines, meaning more performance and less wasted power. And it improves ILP. So Lion Cove is wasting it's resources elsewhere, like the overly big decode for one. Where else is LNC wasting it?
One has to wonder had the spent a little bit more transistor budget on a better branch predictor, and a little bit more on SMT, and wouldn't have botched the ring bus, that we wouldn't have seen a pretty darned fantastic CPU today.
ahh I know why it performs well in CB2024, it’s not cause the P core is awesome, it’s because DRAM bandwidth effects ST by a noticeable margin.
The older Cinebench versions are not dependent on memory for ST scaling.
Well ..... inevitably as you process more information (and rendering is a VERY information heavy workload), you must be able to feed the engine. So I would argue that the P core is, in fact, "awesome" in that it is able to fully utilize all that considerable bandwidth. It also seems to do well in CB2024 MT.
This is one of those times when I really wish Anand was still doing this so he could tell me what to think right now.
Awww yes, Anand was definitely a gem. I remember debating with him in the very early day's of AnandTech. Good guy.