Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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arcky

Junior Member
Oct 21, 2024
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lower latency, higher mem write but lower read and copy

"X3D Turbo Mode" disabled (EXPO profile loaded with all the rest mem settings set to auto):
View attachment 110319

"X3D Turbo Mode" enabled (EXPO profile loaded with all the rest mem settings set to auto):
View attachment 110320
So turbo increased trefi and lowered trfc to get you marginally better latency, and shut off a whole ccd crippling your read/copy bandwidth lol
 

PJVol

Senior member
May 25, 2020
722
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Could these be legit?
 

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Josh128

Senior member
Oct 14, 2022
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744
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Got another 6% in Dawntrail. I havent tweaked my RAM much other than maxing tREFI. At this point I suspect my 6700XT is probably limiting factor.


Seems like I have one of the highest 9900X ST scores in GB also, not that there are that many to choose from.

 

arcky

Junior Member
Oct 21, 2024
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Why in quotes?
It’s these slides from a larger presentation that hardwareluxx attended and for some reason photographed (despite nda language on the literal slides they photographed) at msi offices and then briefly published on their website before removing. There’s errors in the slides (discrepancies between titles and legends), only 3 games tested, and very little transparency into testing conditions, so make of them what you will. ‘Leak’ in the sense that they were intentionally presented by MSI to press but not intended for wider consumption.
 

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PJVol

Senior member
May 25, 2020
722
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‘Leak’ in the sense that they were intentionally presented by MSI to press but not intended for wider consumption.
Ah... gotcha, so it was intentional... )
Anyway, whoever wrote that news, they said 9950x3d has the same l3 laylout as the 7950x3d.
 
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lopri

Elite Member
Jul 27, 2002
13,287
663
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sure

before (EXPO enabled, all timmings auto):

View attachment 110282

After (EXPO enabled, all timmings auto):

View attachment 110283

So as @tsamolotoff said, it sets tREFI to a higher value and tRFC to a lower value.. and thats it

btw @Hitman928, I set "EXPO/XMP high bandwidth support" to disabled, and it was not enabled after enabling this x3d turbo mode thing (and restarting) 🧐
Did you set MEM VPP at 1.35 manually or is it by the board's auto? I am seeing 1.80 when left auto. As a matter of fact I do not even remember I've seen that option in the BIOS.
 

Det0x

Golden Member
Sep 11, 2014
1,336
4,488
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BTW, if it is true and L3 die is below, then why not make SRAM amount > 64 MB? There would be room for more on the die.
Does it matter if they crush the competition 20% or 30% in gaming ? (and they kinda want to keep the die hight the same)
Think this is also the reason for the conservative clocks on the first SKU.. It will be up to us tinkers to push the silicon and really show what it can do
 

inf64

Diamond Member
Mar 11, 2011
3,872
4,591
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Does it matter if they crush the competition 20% or 30% in gaming ? (and they kinda want to keep the die hight the same)
Think this is also the reason for the conservative clocks on the first SKU.. It will be up to us tinkers to push the silicon and really show what it can do
I am hoping that 12 and 16C X3D will have higher clock 3D chiplet clocks. That would be incentive to some potential buyers to opt for higher core count X3D parts, especially if they will have higher OC ceiling on the 3D chiplet.
 

Joe NYC

Platinum Member
Jun 26, 2021
2,625
3,681
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Does it matter if they crush the competition 20% or 30% in gaming ? (and they kinda want to keep the die hight the same)

It does matter. It took very large performance delta for AMD to make inroads to datacenter (with chiplets), and it may take similar delta to make similar inroads in client markets.

As far as height, I was still thinking single layer, but instead of die area of 1/2 of CCD, using same die size for V-Cache as main CCD. Which should fit ~128 MB.

Think this is also the reason for the conservative clocks on the first SKU.. It will be up to us tinkers to push the silicon and really show what it can do

Yeah, it does seem like very conservative clock speed, if there isn't any inherent limiting factor, compared to standard Zen 5 CPUs. Maybe 9850x3d mid-way between Zen 5 and Zen 6 releases.
 

inquiss

Senior member
Oct 13, 2010
219
305
136
It does matter. It took very large performance delta for AMD to make inroads to datacenter (with chiplets), and it may take similar delta to make similar inroads in client markets.

As far as height, I was still thinking single layer, but instead of die area of 1/2 of CCD, using same die size for V-Cache as main CCD. Which should fit ~128 MB.



Yeah, it does seem like very conservative clock speed, if there isn't any inherent limiting factor, compared to standard Zen 5 CPUs. Maybe 9850x3d mid-way between Zen 5 and Zen 6 releases.
More 3D cache isn't going to help in clone markets. It's already the biggest stick. They need to crack the volume markets in OEMs and corporate and you don't do that with a low volume part (that you can't make in high volumes). Especially by making the production even lower volume by adding two stacks.
 

inquiss

Senior member
Oct 13, 2010
219
305
136
With X3D it seems like there is even more reason to push higher memory bandwidth than ever.
I thought the cache on previous versions meant you can get away with lower bandwidth before. An understated part of the value prop for them.

I see the cache chips as a way for AMD to delay IOD improvements while keeping the crown, no?
 
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