High price 😂Well AMD did hint that the 2 CCD V cache parts were “special” no?
What else could make them special?
BTW, if it is true and L3 die is below, then why not make SRAM amount > 64 MB? There would be room for more on the die.
The CPU is getting more work done than before but that is not the reason for the need to speed up memory. The memory clock is in sync with IO and is optimal at different steps of frequency. AMD needs to push memory clock back up to reach another optimal step. As memory clocks raise, latencies decrease, improving performance even more.I thought the cache on previous versions meant you can get away with lower bandwidth before. An understated part of the value prop for them.
I see the cache chips as a way for AMD to delay IOD improvements while keeping the crown, no?
Especially for all data that cannot reside in the limited cache size.As memory clocks raise, latencies decrease, improving performance even more.
Must've made them all sign some NDA and set an embargo date. Nobody has spilled the beans yet on what exactly AMD has shared with them.
Given the ryzen 7 is the only pictured box, it would seem to back the rumor that 9800X3D is the only one releasing now.Must've made them all sign some NDA and set an embargo date. Nobody has spilled the beans yet on what exactly AMD has shared with them.
Has to be directly underneath the CCD for the vias to align otherwise they are using some new packaging technique. And the cache die would be upside down if it's still using the vias to communicate with the CCD. If I have to guess, there is something underneath the cache die that is protecting it from damage and also allowing the heat to dissipate out of it.but will the Cache be on a big Die with lots of dead space or is it 3 dies underneath, one small with cache and 2 silicon pieces for structural support?
So when will the 9800X3D launch and how does it look? Is 7th November the actual availability date (whichbwould mean surprise announcement next week) or is it the announcement date which could mean availability is anywhere from November to even 2025? I mean 7800X3D announcement was early January 2023 and launch was in April.
And then, how will it look like? Looks like Cache below CCD is set in stone now, but will the Cache be on a big Die with lots of dead space or is it 3 dies underneath, one small with cache and 2 silicon pieces for structural support?
Have power supply TSVs to the cache die been seen on die shots? I wonder if the cache die is powered from below or from the CCD.
Have power supply TSVs to the cache die been seen on die shots? I wonder if the cache die is powered from below or from the CCD.
Zen 5 die: TSV's to the 64 MB X3D L3 cache:
It simply must have enough and well distributed TSV's...
It looks like a all the TSV's providing the power to the X3D L3 die are using an MIM decoupling capacitor for each power and ground pair of TSV's leading to something like an extra ~8500 power/ground TSV's. Under each black square should be two TSV's.
Original die photos: https://www.flickr.com/photos/130561288@N04/
View attachment 108838
Well, the power delivery to the cores is a much bigger issue than power delivery to V-Cache. And Hans de Vries found some TSVs in the core area that could be delivering this power from the die below.
As far as power delivery to V-Cache, it does not have to come from CCD above, it can come directly from below. This could explain fewer TSVs that High Yield counted going from Ring Bus / L3 area CCD to V-Cache die.
I would find it entirely incredible for the CCD to be powered through the TSVs. It needs a lot of current, and the resistance on that would suck. If the CCD is on top, I suspect it would be powered from above. This is a radical change, but everyone is working on that anyway because of BSPD, and I don't see why TSMC couldn't have the easy parts already working in advance for that.
If they power it from the top, they'd have to go back to wire bonds, which I highly doubt is the approach they've taken. It is actually less resistance by powering from underneath because you don't have to go through all the metal layers to get from the top of the chip to the devices.
In the Arrow Lake reviews, the reviewers mentioned 9800x3d reviews in matter of days. So I am guessing reviews in upcoming week, and availability could still be November 7.
You still have to go to the top. AMD CPUs are powered from MIMCAPs that are in the uppermost metal layers. So if you powered it through a TSV, you need to push the power all the way to the other side of the chip, and then all the way back down. When they do backside power, they can move those caps on the backside too. But the vCache variant CPUs use the same die.
Also I think you are dramatically overestimating how good the TSVs are for moving power. To have the kind of power delivery that matches what they are already doing, they'd need them a lot denser than what they are on die.
But not proportionally. DRAM latency is rather stagnant.As memory clocks raise, latencies decrease, improving performance even more.
https://pbs.twimg.com/media/GaLTfYuagAAeh37?format=jpg&name=large
If there's no announcement being made then what is this invitation letter for??
Nobody? Or *almost* nobody?Must've made them all sign some NDA and set an embargo date. Nobody has spilled the beans yet on what exactly AMD has shared with them.
Looks like Cache below CCD is set in stone now, but will the Cache be on a big Die with lots of dead space or is it 3 dies underneath, one small with cache and 2 silicon pieces for structural support?
But it still could, with metal layers and thermal vias close to CCD hotspots, couldn't it?I was speculating about that. The structural support dies in previous gen V-Cache also offered better thermal connectivity, so it offered one advantage, at cost of more complex assembly.
A die underneath does not offer this advantage, […]
As for TSVs, they have current limits lower than their geometries and conductance would suggest due to structural concerns in the bonding, but they can still handle way more power than the vias on the front side. BSPD processes use TSVs for all of the power delivery.
What if 9950X3D CCD is sandwiched between V-cache dies?The TSVs would connect to nothing, unless I'm missing something?
Not identical, as it is apparently C0 silicon for VCache models.You still have to go to the top. AMD CPUs are powered from MIMCAPs that are in the uppermost metal layers. So if you powered it through a TSV, you need to push the power all the way to the other side of the chip, and then all the way back down. When they do backside power, they can move those caps on the backside too. But the vCache variant CPUs use the same die.
Also I think you are dramatically overestimating how good the TSVs are for moving power. To have the kind of power delivery that matches what they are already doing, they'd need them a lot denser than what they are on die.
Cores: 8 (8C)
Threads: 16
Turbo Clock: 5.20GHz
Base Clock: 4.70GHz
TDP: 120W
Graphics: yes (AMD Radeon Graphics)
Socket: AMD AM5 (LGA1718)
chipset suitability: A620, A620A, B650, B650E, PRO 600, PRO 665, X600, X670, X670E, X870E
Codename: Granite Ridge
Architecture: Zen 5
Manufacturing Process: TSMC 4nm (CPU), TSMC 6nm (I/O)
L2 cache: 8MB (8x 1MB)
L3 cache: 96MB (32MB + 64MB 3D-cache)
Memory controller: Dual Channel DDR5, max. 192GB
Memory compatibility: max. DDR5-5600 (PC5-44800, 89.6GB/s)
Memory compatibility extended (DIMM): DDR5-5600 (1DPC/1R), DDR5-5600 (1DPC/2R), DDR5-3600 (2DPC/1R), DDR5-3600 (2DPC/2R)
ECC support: yes
SMT: yes
Remote management: no
Unlocked: yes
CPU-Features: AES-NI, AMD-V, AVX, AVX-512, AVX2, FMA3, MMX(+), SHA, SSE, SSE2, SSE3, SSE4.1, SSE4.2, SSE4a, x86-64
Scalability: 1 socket (1S)
PCIe Lanes: 28x PCIe 5.0 (available: 24)
chipset Interface: PCIe 4.0 x4
iGPU-Model: AMD Radeon Graphics
iGPU-Clock: 2.20GHz
iGPU-Units: 2CU/128SP
iGPU-Architecture: RDNA 2, Codename "Granite Ridge"
iGPU Interface: DP 2.0, HDMI 2.1
iGPU-Features: 4x display support, AMD Eyefinity, AMD FreeSync 2, AV1 decode, H.265 encode/decode, VP9 decode, DirectX 12.1, OpenGL 4.5, Vulkan 1.0
iGPU processing Power: 0.56 TFLOPS (FP32)
Scope of Delivery: without CPU cooler
Launch: 2024/Q4 (7.11.2024)
Segment: desktop (Mainstream)
Stepping: GNR-B0
Max Temperature: 95°C (Tjmax)
Warranty: 3 years at AMD® Boxed-processors (Info EN)
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