Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

Page 856 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

MadRat

Lifer
Oct 14, 1999
11,950
272
126
I thought the cache on previous versions meant you can get away with lower bandwidth before. An understated part of the value prop for them.

I see the cache chips as a way for AMD to delay IOD improvements while keeping the crown, no?
The CPU is getting more work done than before but that is not the reason for the need to speed up memory. The memory clock is in sync with IO and is optimal at different steps of frequency. AMD needs to push memory clock back up to reach another optimal step. As memory clocks raise, latencies decrease, improving performance even more.
 

Philste

Senior member
Oct 13, 2023
259
453
96
So when will the 9800X3D launch and how does it look? Is 7th November the actual availability date (whichbwould mean surprise announcement next week) or is it the announcement date which could mean availability is anywhere from November to even 2025? I mean 7800X3D announcement was early January 2023 and launch was in April.

And then, how will it look like? Looks like Cache below CCD is set in stone now, but will the Cache be on a big Die with lots of dead space or is it 3 dies underneath, one small with cache and 2 silicon pieces for structural support?
 
Jul 27, 2020
20,420
14,090
146
but will the Cache be on a big Die with lots of dead space or is it 3 dies underneath, one small with cache and 2 silicon pieces for structural support?
Has to be directly underneath the CCD for the vias to align otherwise they are using some new packaging technique. And the cache die would be upside down if it's still using the vias to communicate with the CCD. If I have to guess, there is something underneath the cache die that is protecting it from damage and also allowing the heat to dissipate out of it.
 

Joe NYC

Platinum Member
Jun 26, 2021
2,625
3,681
106
So when will the 9800X3D launch and how does it look? Is 7th November the actual availability date (whichbwould mean surprise announcement next week) or is it the announcement date which could mean availability is anywhere from November to even 2025? I mean 7800X3D announcement was early January 2023 and launch was in April.

In the Arrow Lake reviews, the reviewers mentioned 9800x3d reviews in matter of days. So I am guessing reviews in upcoming week, and availability could still be November 7.

And then, how will it look like? Looks like Cache below CCD is set in stone now, but will the Cache be on a big Die with lots of dead space or is it 3 dies underneath, one small with cache and 2 silicon pieces for structural support?

I was speculating about that. The structural support dies in previous gen V-Cache also offered better thermal connectivity, so it offered one advantage, at cost of more complex assembly.

A die underneath does not offer this advantage, and if there are 3 pieces of silicon, it would still have higher complexity and higher cost of assembly.

Then, the comparison, a single piece of silicon starts to look much better, bypassing a lot of this complexity, and coming closer to equaling the cost of larger silicon area of a full die underneath.

And if there is a full 70 mm2 die in place, hopefully AMD would take full advantage of it. One of which could be more SRAM than 64 MB.
 

Joe NYC

Platinum Member
Jun 26, 2021
2,625
3,681
106
Have power supply TSVs to the cache die been seen on die shots? I wonder if the cache die is powered from below or from the CCD.

Well, the power delivery to the cores is a much bigger issue than power delivery to V-Cache. And Hans de Vries found some TSVs in the core area that could be delivering this power from the die below.

As far as power delivery to V-Cache, it does not have to come from CCD above, it can come directly from below. This could explain fewer TSVs that High Yield counted going from Ring Bus / L3 area CCD to V-Cache die.
 

moinmoin

Diamond Member
Jun 1, 2017
5,094
8,098
136
Have power supply TSVs to the cache die been seen on die shots? I wonder if the cache die is powered from below or from the CCD.

@Hans de Vries found following details on the Zen 5 dies that indicate there are power vias through the cores to the cache dies which make it much more likely that the cache die is sitting on top of the CCD again.

Or those power TSVs are used for something completely different, who knows.

Zen 5 die: TSV's to the 64 MB X3D L3 cache:

It simply must have enough and well distributed TSV's...

It looks like a all the TSV's providing the power to the X3D L3 die are using an MIM decoupling capacitor for each power and ground pair of TSV's leading to something like an extra ~8500 power/ground TSV's. Under each black square should be two TSV's.

Original die photos: https://www.flickr.com/photos/130561288@N04/

View attachment 108838
 

Tuna-Fish

Golden Member
Mar 4, 2011
1,494
2,059
136
Well, the power delivery to the cores is a much bigger issue than power delivery to V-Cache. And Hans de Vries found some TSVs in the core area that could be delivering this power from the die below.

As far as power delivery to V-Cache, it does not have to come from CCD above, it can come directly from below. This could explain fewer TSVs that High Yield counted going from Ring Bus / L3 area CCD to V-Cache die.

I would find it entirely incredible for the CCD to be powered through the TSVs. It needs a lot of current, and the resistance on that would suck. If the CCD is on top, I suspect it would be powered from above. This is a radical change, but everyone is working on that anyway because of BSPD, and I don't see why TSMC couldn't have the easy parts already working in advance for that.
 

Hitman928

Diamond Member
Apr 15, 2012
6,330
11,136
136
I would find it entirely incredible for the CCD to be powered through the TSVs. It needs a lot of current, and the resistance on that would suck. If the CCD is on top, I suspect it would be powered from above. This is a radical change, but everyone is working on that anyway because of BSPD, and I don't see why TSMC couldn't have the easy parts already working in advance for that.

If they power it from the top, they'd have to go back to wire bonds, which I highly doubt is the approach they've taken. It is actually less resistance by powering from underneath because you don't have to go through all the metal layers to get from the top of the chip to the devices. Going through a few metal layers + TSV (which are very low resistance) is the lower resistance path. Assuming this is what they've done, the big question is what layer does the TSV connect to in the CCD? This will determine the impact it has on density and the higher up it connects, the more resistance it will have (still should be lower than top fed power lines).
 

Tuna-Fish

Golden Member
Mar 4, 2011
1,494
2,059
136
If they power it from the top, they'd have to go back to wire bonds, which I highly doubt is the approach they've taken. It is actually less resistance by powering from underneath because you don't have to go through all the metal layers to get from the top of the chip to the devices.

You still have to go to the top. AMD CPUs are powered from MIMCAPs that are in the uppermost metal layers. So if you powered it through a TSV, you need to push the power all the way to the other side of the chip, and then all the way back down. When they do backside power, they can move those caps on the backside too. But the vCache variant CPUs use the same die.

Also I think you are dramatically overestimating how good the TSVs are for moving power. To have the kind of power delivery that matches what they are already doing, they'd need them a lot denser than what they are on die.
 

jpiniero

Lifer
Oct 1, 2010
15,292
5,806
136
In the Arrow Lake reviews, the reviewers mentioned 9800x3d reviews in matter of days. So I am guessing reviews in upcoming week, and availability could still be November 7.

I could see reviews next week, mainly to get ahead of the election news cycle. The only problem might be is that Apple is doing announcements too.
 

Hitman928

Diamond Member
Apr 15, 2012
6,330
11,136
136
You still have to go to the top. AMD CPUs are powered from MIMCAPs that are in the uppermost metal layers. So if you powered it through a TSV, you need to push the power all the way to the other side of the chip, and then all the way back down. When they do backside power, they can move those caps on the backside too. But the vCache variant CPUs use the same die.

Also I think you are dramatically overestimating how good the TSVs are for moving power. To have the kind of power delivery that matches what they are already doing, they'd need them a lot denser than what they are on die.

Usually MIMcaps are in the middle layers as they require special dielectrics and they want to be able to offer them on process options that have fewer metal layers. Granted, my experience is on larger nodes, these advanced nodes are so hyper specialized for digital circuits that they may have pushed them higher. Either way, the issue is that if you bring in power from the top, you'll need either bond wires (impractical) or the top die is still flip chip, but if that is the case, then what are the TSVs doing in the CCD at all? In my head, I was assuming the bottom die would have the caps, like they do in BSPD but, admittedly, I was only considering the die as a V-cache product and didn't think about it being the same die they use for the vanilla products which kind of eliminates the option for backside power delivery.

As for TSVs, they have current limits lower than their geometries and conductance would suggest due to structural concerns in the bonding, but they can still handle way more power than the vias on the front side. BSPD processes use TSVs for all of the power delivery. They will be higher density than what they currently have but will also have lower current limits per TSV. With both V-cache and vanilla products using the same CCD, I'm at a loss for what the TSVs are doing on the CCD if it is indeed now the top die and it's flip chip. The TSVs would connect to nothing, unless I'm missing something?
 
Last edited:

StefanR5R

Elite Member
Dec 10, 2016
5,968
8,941
136
As memory clocks raise, latencies decrease, improving performance even more.
But not proportionally. DRAM latency is rather stagnant.

https://pbs.twimg.com/media/GaLTfYuagAAeh37?format=jpg&name=large

If there's no announcement being made then what is this invitation letter for??
Must've made them all sign some NDA and set an embargo date. Nobody has spilled the beans yet on what exactly AMD has shared with them.
Nobody? Or *almost* nobody?
There is the alleged AMD slide which was posted by VideoCardz, of which e.g. ComputerBase went as far as to call it "apparently" (or "evidently" even, their original wording is augenscheinlich) "originating directly from AMD".

[Edit: ComputerBase's headline even speaks of "official performance data", but ComputerBase does produce click-bait headlines on occasions. On the other hand, their usual policy of reporting on rumors is, AFAIK, not to report on sketchy rumors from sketchy outlets, to put clear cautionary notes around rumors which look more or less reasonable to them and come from outlets with good track record but which they cannot investigate themselves, and to mostly forego such notes if the rumor aligns with what they already have learned themselves under NDA.]

Looks like Cache below CCD is set in stone now, but will the Cache be on a big Die with lots of dead space or is it 3 dies underneath, one small with cache and 2 silicon pieces for structural support?
I was speculating about that. The structural support dies in previous gen V-Cache also offered better thermal connectivity, so it offered one advantage, at cost of more complex assembly.

A die underneath does not offer this advantage, […]
But it still could, with metal layers and thermal vias close to CCD hotspots, couldn't it?
 
Last edited:

StefanR5R

Elite Member
Dec 10, 2016
5,968
8,941
136
PS,
as a reminder, the current 3D V-cache™ implementation (Zen 3's, and certainly Zen 4's too) actually involves two kinds of structural silicon: The two little and thin pieces adjacent to the cache silicon, which are also pictured in the well known marketing material from AMD, and a large thick slab of structural silicon placed across all three thin pieces, which has never been shown in marketing slides but in an ISSCC 2022 presentation.


(source: https://www.ithome.com.tw/tech/151041 and other ISSCC 2022 reports)
 

Tuna-Fish

Golden Member
Mar 4, 2011
1,494
2,059
136
As for TSVs, they have current limits lower than their geometries and conductance would suggest due to structural concerns in the bonding, but they can still handle way more power than the vias on the front side. BSPD processes use TSVs for all of the power delivery.

Yes, but they have a lot more TSVs than what Zen5 does. The better BSPD implementations have ~a TSV for every transistor, literally billions of them per die. Zen5 has ~tens of thousands.
 

lightmanek

Senior member
Feb 19, 2017
445
975
136
You still have to go to the top. AMD CPUs are powered from MIMCAPs that are in the uppermost metal layers. So if you powered it through a TSV, you need to push the power all the way to the other side of the chip, and then all the way back down. When they do backside power, they can move those caps on the backside too. But the vCache variant CPUs use the same die.

Also I think you are dramatically overestimating how good the TSVs are for moving power. To have the kind of power delivery that matches what they are already doing, they'd need them a lot denser than what they are on die.
Not identical, as it is apparently C0 silicon for VCache models.
 

sl0519

Member
Aug 10, 2024
32
86
51
From reddit: 9800x3D specifications appear on german price comparison website

Full specs:
Cores: 8 (8C)
Threads: 16
Turbo Clock: 5.20GHz
Base Clock: 4.70GHz
TDP: 120W
Graphics: yes (AMD Radeon Graphics)
Socket: AMD AM5 (LGA1718)
chipset suitability: A620, A620A, B650, B650E, PRO 600, PRO 665, X600, X670, X670E, X870E
Codename: Granite Ridge
Architecture: Zen 5
Manufacturing Process: TSMC 4nm (CPU), TSMC 6nm (I/O)
L2 cache: 8MB (8x 1MB)
L3 cache: 96MB (32MB + 64MB 3D-cache)
Memory controller: Dual Channel DDR5, max. 192GB
Memory compatibility: max. DDR5-5600 (PC5-44800, 89.6GB/s)
Memory compatibility extended (DIMM): DDR5-5600 (1DPC/1R), DDR5-5600 (1DPC/2R), DDR5-3600 (2DPC/1R), DDR5-3600 (2DPC/2R)
ECC support: yes
SMT: yes
Remote management: no
Unlocked: yes
CPU-Features: AES-NI, AMD-V, AVX, AVX-512, AVX2, FMA3, MMX(+), SHA, SSE, SSE2, SSE3, SSE4.1, SSE4.2, SSE4a, x86-64
Scalability: 1 socket (1S)
PCIe Lanes: 28x PCIe 5.0 (available: 24)
chipset Interface: PCIe 4.0 x4
iGPU-Model: AMD Radeon Graphics
iGPU-Clock: 2.20GHz
iGPU-Units: 2CU/128SP
iGPU-Architecture: RDNA 2, Codename "Granite Ridge"
iGPU Interface: DP 2.0, HDMI 2.1
iGPU-Features: 4x display support, AMD Eyefinity, AMD FreeSync 2, AV1 decode, H.265 encode/decode, VP9 decode, DirectX 12.1, OpenGL 4.5, Vulkan 1.0
iGPU processing Power: 0.56 TFLOPS (FP32)
Scope of Delivery: without CPU cooler
Launch: 2024/Q4 (7.11.2024)
Segment: desktop (Mainstream)
Stepping: GNR-B0
Max Temperature: 95°C (Tjmax)
Warranty: 3 years at AMD® Boxed-processors (Info EN)
Last price update: -
Listed since: 2024-10-21, 5:33pm

So 5.2 max boost is pretty much confirmed. If thermal restraint was lifted, why is boost still .3 Ghz down from non V-cache model??
 
Last edited:
Reactions: Tlh97 and arcky
sale-70-410-exam    | Exam-200-125-pdf    | we-sale-70-410-exam    | hot-sale-70-410-exam    | Latest-exam-700-603-Dumps    | Dumps-98-363-exams-date    | Certs-200-125-date    | Dumps-300-075-exams-date    | hot-sale-book-C8010-726-book    | Hot-Sale-200-310-Exam    | Exam-Description-200-310-dumps?    | hot-sale-book-200-125-book    | Latest-Updated-300-209-Exam    | Dumps-210-260-exams-date    | Download-200-125-Exam-PDF    | Exam-Description-300-101-dumps    | Certs-300-101-date    | Hot-Sale-300-075-Exam    | Latest-exam-200-125-Dumps    | Exam-Description-200-125-dumps    | Latest-Updated-300-075-Exam    | hot-sale-book-210-260-book    | Dumps-200-901-exams-date    | Certs-200-901-date    | Latest-exam-1Z0-062-Dumps    | Hot-Sale-1Z0-062-Exam    | Certs-CSSLP-date    | 100%-Pass-70-383-Exams    | Latest-JN0-360-real-exam-questions    | 100%-Pass-4A0-100-Real-Exam-Questions    | Dumps-300-135-exams-date    | Passed-200-105-Tech-Exams    | Latest-Updated-200-310-Exam    | Download-300-070-Exam-PDF    | Hot-Sale-JN0-360-Exam    | 100%-Pass-JN0-360-Exams    | 100%-Pass-JN0-360-Real-Exam-Questions    | Dumps-JN0-360-exams-date    | Exam-Description-1Z0-876-dumps    | Latest-exam-1Z0-876-Dumps    | Dumps-HPE0-Y53-exams-date    | 2017-Latest-HPE0-Y53-Exam    | 100%-Pass-HPE0-Y53-Real-Exam-Questions    | Pass-4A0-100-Exam    | Latest-4A0-100-Questions    | Dumps-98-365-exams-date    | 2017-Latest-98-365-Exam    | 100%-Pass-VCS-254-Exams    | 2017-Latest-VCS-273-Exam    | Dumps-200-355-exams-date    | 2017-Latest-300-320-Exam    | Pass-300-101-Exam    | 100%-Pass-300-115-Exams    |
http://www.portvapes.co.uk/    | http://www.portvapes.co.uk/    |