Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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Gideon

Golden Member
Nov 27, 2007
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32 MB on-die L3$ is already quite a lot for 8c/16t for most applications. The next time they spend more CCD area on cache, they might perhaps spend it on L2$ rather than L3$.
I really wish the x86 world (for desktop and mobile) would also offer similar tiled L2 as Qualcomm and Apple:

Snapdragon X has a 96KB L1 and 12MB L2 per core cluster (4 x 3MB slices, but a single core can use all 12MB), with nearly identical latency to AMD’s private 1MB L2.




Oryon uses an Apple-like caching strategy. A large 96 KB L1 and relatively fast L2 with 20 cycles of latency together mean Oryon doesn’t need a mid-level cache. Firestorm has a bigger 128 KB L1, but Oryon’s L1 is still much larger than the 32 or 48 KB L1 caches in Zen 4 or Redwood Cove.


AMD has a 1 MB L2 mid-level cache private to each core, then a 16 MB L3. That setup makes it easier to increase caching capacity, because the L2 cache can insulate the core from L3 latency. However, that advantage is minimal for mobile Zen 4 parts, which max out at 16 MB of L3. Oryon therefore provides competitive latency especially as accesses spill out of Zen 4’s L2. Meteor Lake follows a similar caching strategy to Zen 4, but has more caching capacity at the expense of higher latency.

I'm not sure what the optimal cache hierarchy would be for desktop chips, but the current design sure seems nonoptimal for client workloads (it makes much more sense on server).

Could you imagine the gaming performance of an AMD chip that would have:
  • 24MB tiled L2 (12MB + 12MB shared by 4 cores each, if it's required to not regress in latency)
  • 96 - 128MB L3 (3D cache)
  • 2nd gen chiplets (similar to Strix Halo) with full-width memory bandwidth per CCD and faster FCLK support (2600+Mhz)

Ideally it should also have 3-4 memory channels using aggressive low-latency CAMM2 modules, but you can't have it all I guess (that would need a new socket) ...


TL;DR:

A 1MB - 3MB private L2 only makes sense if it provides 2-3x better latency or bandwidth than a 12MB shared, tiled L2. Otherwise, it’s a waste of SRAM potential, IMO.
 
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Kepler_L2

Senior member
Sep 6, 2020
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MS_AT

Senior member
Jul 15, 2024
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I really wish the x86 world (for desktop and mobile) would also offer similar tiled L2 as Qualcomm and Apple:

Snapdragon X has a 96KB L1 and 12MB shared L2 per 4 cores (4x 3MB slices but a single core can use all 12MB), but it has the same latency than AMD private 1MB L2.
It does have the similar latency in cycles, but worse absolute latency [ns].
 

Tuna-Fish

Golden Member
Mar 4, 2011
1,505
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I really wish the x86 world (for desktop and mobile) would also offer similar tiled L2 as Qualcomm and Apple:

Snapdragon X has a 96KB L1 and 12MB L2 per core cluster (4 x 3MB slices, but a single core can use all 12MB), with nearly identical latency to AMD’s private 1MB L2.

At what clocks? Cache latency measured in clock cycles is identical, but this was only possible for them to implement because they had twice the wall clock time to do so.

The AMD L2 is extremely tight, you are not increasing it's size at all without a latency regression. You are absolutely not sharing it with anything without a latency regression.
 

StefanR5R

Elite Member
Dec 10, 2016
6,057
9,107
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This is supposed to be "official spec sheet". One thing that's missing from the previous "official spec sheet" is DDR-6000 support:

Already posted in #21,400 and #21,401. And it hasn't become any more official than it was at the time of #21,405 and #21,411. :-) IOW, it's quite possibly not a leak, but likely just a rehash of previous leaks and wannabe-leaks.

It's an Austrian price comparison site. They are unlikely to receive 1st party spec sheets before product launch.
 
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StefanR5R

Elite Member
Dec 10, 2016
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136
V-Cache isn't visible on retail silicon. Those shots of Lisa holding X3D with visible dies is without the top supporting silicon.
To be fair, it's not just the very lowest end of online journalism who don't get it. ComputerBase.de have been trolled ;-) by AMD in the same way. "... the 3D cache, which can otherwise be seen with the naked eye, ..."

(Edit: CB were made aware of this fact and corrected their article now.)
 
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coercitiv

Diamond Member
Jan 24, 2014
6,761
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This writing is either ousourced to Malaysia or fake.
or both
You can add LLM generated as well:
Introducing the AMD Ryzen 7 9800X3D, the latest powerhouse in gaming and multitasking performance, featuring revolutionary 3D V-Cache technology. Elevate your computing experience with unbeatable speeds and unparalleled efficiency.
  • Next-Gen 3D V-Cache Technology: Enhanced performance with up to 96MB of L3 cache.
  • Unmatched Gaming Performance: Boosts gaming performance by up to 26% over the previous generation.
  • Higher Clock Speeds: Achieves up to 5.2GHz for lightning-fast processing.
  • Improved Thermal Performance: Better cooling efficiency for sustained high performance.
  • Zen 5 Architecture: Built on the latest Zen 5 core architecture for superior efficiency and power.
  • AM5 Compatibility: Fully compatible with the AM5 platform, supporting PCIe Gen 5 and DDR5 memory.
  • Multi-Threaded Excellence: Ideal for multitasking and content creation with 8 cores and 16 threads.
  • Future-Proof Design: Ready for upcoming technologies and applications.
 
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