Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

Hulk · Oct 29, 2024

Based on the benches below it seems as though the L2 is where ARL is falling behind RPL, yes?

AcrosTinus · Oct 29, 2024

DavidC1 said:
Ok, but still.

-The first excuse was that ARM could never catch x86 cores even in per clock performance. Well, they did.
-The second excuse is that performance is perf/clock x clocks. Well, the M4 beats x86 processors in absolute ST performance.

We're at the third point now, which is MT performance against 200W+ processors. And I'm conveniently ignoring the much, much low power required to achieve that performance.

Like, slap Conroe vs Netburst comparison silly. Apple would have done to "Conroe" what Conroe was doing to Netburst. I knew after I got out of the silly x86 duopoly bubble mindset, after about Apple A8 I realized that what Intel achieved with Conroe/Merom would be blown away very soon.

The real truth is none of those excuses mattered, and it's simply Apple(and ARM in general) doing lot better in execution.

I am waiting for the benchmarks, if the Cinebench score is at 14700K level, I will be buying it, it is a no brainer device if the performance is right.

AcrosTinus · Oct 29, 2024

Hulk said:
I see MC has them for $420 but where did you pick one up for $360?

The 14900K is future proofed with Intel's extended warranty. If it fails you get a new one or reimbursed. If it makes 5 years then good on you!

A friend bought a 14900K 3 Months ago and never finished building his system, the benefits of having hardware friends in whatsapp, one question into the group and you might even get hardware for free.

Yeah the prolonged warranty lets me ride out the 14900K into the future, hopefully all bugs are squashed by then.

511 · Oct 30, 2024

poke01 said:
Here is another kicker Apple beat Intel to include proper Thunderbolt 5 on desktop today and most likely tomorrow on a laptop. The full spec 120GB/s.

What IS Intel doing? They used to be at the fore front of USB/thunderbolt standards. You can tell Arrow lake was delayed by the fact it does not support TB5.
There is a Razer Balde that supports TB5 but thats only on 1 port @ 80GB/s. The Razer laptop just use a discrete chip, Barlow ridge and unlike TB4 its not baked in.

This shows how bad they have fallen anyway intel is the sole manufacturer for TB IC retimers have to be bought from Intel just released it to be first to ThunderBolt 5 in name

511 · Oct 30, 2024

AcrosTinus said:
I am waiting for the benchmarks, if the Cinebench score is at 14700K level, I will be buying it, it is a no brainer device if the performance is right.

I think it should be with M4 Max the power consumption is increasing though if i had to guess around 80W

511 · Oct 30, 2024

M4 ~ M3 Max level performance which is around 1600 r24 while consuming the same 52-55W iirc btw apple lists it as CPU Power not package power right?

poke01 · Oct 30, 2024

511 said:
This shows how bad they have fallen anyway intel is the sole manufacturer for TB IC retimers have to be bought from Intel just released it to be first to ThunderBolt 5 in name

Apple has their own TB retimers since M2. https://www.tomshardware.com/news/apple-amd-removes-intel-silicon

DavidC1 · Oct 30, 2024

Hulk said:
Based on the benches below it seems as though the L2 is where ARL is falling behind RPL, yes?

View attachment 110559

View attachment 110560

Yea L2 has lot less bandwidth. So they enlarged the L2 cache but now has half the bandwidth in Read. Copy is Read + Write so naturally it'll be lower.

Don't forget the fabric affecting memory latency. L3 latency based on AIDA seems to be ok.

StinkyPinky said:
This may be the worst launch Intel has done since the Pentium 4. Granted Haswell to Kaby Lake weren't up to much, but at least it didn't freaking regress.

Here's a key difference. Pentium 4 had amazing engineering and ideas on it, just that the ideology behind it sucked. Trace Cache, Double pumped ALU. They demonstrated an ALU at 10GHz. They had undisputed process leadership. Idontcare and many other people were talking about how SEM shots of Intel's transistors were clean and neat, while others were more "messy". It was amazing.

They are losing that base. They used to lead in memory standard. It was Intel chips that supported the fastest memory speeds, it was Intel that supported the latest IO standards(PCI Express, USB). Some were flawed like BTX, but again computing was spearheaded by Intel.

I'm not happy at all saying this. They are losing the foundation they used to have. Yes, they still were led in a stupid direction, but the people under it made it work.

@igor_kavinski The common belief is that Swan was brought in to stabilize the company, so Gelsinger could fix it. They needed someone to manage after Kraznich was kicked out abruptly.

naukkis · Oct 30, 2024

DavidC1 said:
Yea L2 has lot less bandwidth. So they enlarged the L2 cache but now has half the bandwidth in Read. Copy is Read + Write so naturally it'll be lower.

That's not the whole case. LC L2 is actually L3, there's that intermediate cache level there. Adding cache levels have always drawbacks but increasing L2 lower level cache from 48KB to 192KB should reduce L2 bandwidth requirement for usual workload over factor 2, which makes it possible sacrifice L2 bandwidth for bigger size.

DavidC1 · Oct 30, 2024

naukkis said:
That's not the whole case. LC L2 is actually L3, there's that intermediate cache level there. Adding cache levels have always drawbacks but increasing L2 lower level cache from 48KB to 192KB should reduce L2 bandwidth requirement for usual workload over factor 2, which makes it possible sacrifice L2 bandwidth for bigger size.

I forgot about the hierarchy change in Lion Cove.

So many changes for so little.

MS_AT · Oct 30, 2024

DavidC1 said:
This is why I keep saying, the mini-Netburst era needs to go away, both at AMD and Intel. Back down on the ridiculous clocks, get rid of the uop cache since now they have an alternative that's more efficient.

Efficient in which terms? Power efficient? Space efficient? We haven't seen three-way decode clusters in action in high performance oriented designs yet. And Skymont's goal is performance per area, I would guess, while uop cache is doing fine in Zen5.

poke01 said:
Looks like RAM speed/bandwidth does play a role in CB2024.

Well, yes. That was conclusion from C&C review of CB2024 from October 2023. This together with little use of SIMD in instructions mix explains why Arrow Lake and Apple M chips are doing well there, though for M chips we would need somebody check the assembly, to verify the instruction mix is placing the same emphasis on scalar operations.

igor_kavinski · Oct 30, 2024

I think Arrow Lake shows why CB2024 should never ever be taken seriously as a benchmark ever again. And to an extent, Geekbench too. Scores of both failed to predict serious regression inducing issues/bugs in ARL's design.

naukkis · Oct 30, 2024

MS_AT said:
This together with little use of SIMD in instructions mix explains why Arrow Lake and Apple M chips are doing well there, though for M chips we would need somebody check the assembly, to verify the instruction mix is placing the same emphasis on scalar operations.

CB gives actually very realistic use-case of SIMD instructions use. Some 128-bits are used, about 6% of instructions in CB2024 which other way states that about 25% of it's code is vectorizable. Longer vectors aren't useful at all. And it's safe to assume that ray tracer engine is pretty well optimized. x86 vendors should also optimize their designs to those general-usage patterns instead of long-vector HPC use cases. If they don't gap to ARM designs will be widening generation after generation. Skymont is actually sane general use case-optimized x86 design - hopefully Intel won't ruin it too in next generations by widening SIMD-units.

DAPUNISHER · Oct 30, 2024

Based on Jay's vid, the 285K with CUDIMM and a good board is going to be a ton of fun for the hot rodder crowd. Looking forward to less conventional testing, like how it does in the Fallout 4 draw calls; that's a cool thread here.

511 · Oct 30, 2024

naukkis said:
CB gives actually very realistic use-case of SIMD instructions use. Some 128-bits are used, about 6% of instructions in CB2024 which other way states that about 25% of it's code is vectorizable. Longer vectors aren't useful at all. And it's safe to assume that ray tracer engine is pretty well optimized. x86 vendors should also optimize their designs to those general-usage patterns instead of long-vector HPC use cases. If they don't gap to ARM designs will be widening generation after generation. Skymont is actually sane general use case-optimized x86 design - hopefully Intel won't ruin it too in next generations by widening SIMD-units.

Widening of SIMD unit is undeniably going to happen to be able to handle 512bit Vectors from 256bit currently
AVX10 clears the fragmentation issues and removal of instructions whenever someone wants

naukkis · Oct 30, 2024

511 said:
Widening of SIMD unit is undeniably going to happen to 512Bits AVX10 clears the fragmentation issues

No, AVX10 just brings AVX512-instructions support to shorter registers without need to support 512 bits. So desktop-mobile could have AVX128 design.

MS_AT · Oct 30, 2024

igor_kavinski said:
I think Arrow Lake shows why CB2024 should never ever be taken seriously as a benchmark ever again. And to an extent, Geekbench too. Scores of both failed to predict serious regression inducing issues/bugs in ARL's design.

I disagree. You just need to keep in mind what they are measuring when looking at the results as it is impossible to create one benchmark to rule them all.

naukkis said:
CB gives actually very realistic use-case of SIMD instructions use. Some 128-bits are used, about 6% of instructions in CB2024 which other way states that about 25% of it's code is vectorizable. Longer vectors aren't useful at all. And it's safe to assume that ray tracer engine is pretty well optimized. x86 vendors should also optimize their designs to those general-usage patterns instead of long-vector HPC use cases. If they don't gap to ARM designs will be widening generation after generation. Skymont is actually sane general use case-optimized x86 design - hopefully Intel won't ruin it too in next generations by widening SIMD-units.

is the 25% statement from Maxon? As the whole benchmark seems to be written with idea of highest portability, first. The wider the SIMD the less instructions to decode, thus I guess why they opt to move in that direction

naukkis said:
No, AVX10 just brings AVX512-instructions support to shorter registers without need to support 512 bits. So desktop-mobile could have AVX128 design.

The AVX10/128 was dropped. Desktop will stick with AVX10/256 [this make using 128b possible, but requires that 256 be supported], while server will use AVX10/512. This is a guess based on Intel's current policy. But this will anyway bring improvements, by porting AVX512 features without requiring 512b registers.

poke01 · Oct 30, 2024

igor_kavinski said:
I think Arrow Lake shows why CB2024 should never ever be taken seriously as a benchmark ever again. And to an extent, Geekbench too. Scores of both failed to predict serious regression inducing issues/bugs in ARL's design.

This doesn't make sense cause SPEC and R23 also showed that Arrow Lake made a generational increase over Raptor Lake.
Do we also disregard SPEC and R23 because these also failed to show regression in Arrow Lake?

IMO, these benchmarks should be taken as a guide and let real world productivity/gaming tests show the increases for your workflows.

igor_kavinski · Oct 30, 2024

poke01 said:
This doesn't make sense cause SPEC and R23 also showed that Arrow Lake made a generational increase over Raptor Lake.

Maybe the next SPEC fixes that.

511 · Oct 30, 2024

naukkis said:
No, AVX10 just brings AVX512-instructions support to shorter registers without need to support 512 bits. So desktop-mobile could have AVX128 design.

Yes that was the main point and the issue with different CUPID of instruction it will provide a better baseline than AVX-512 ever was in terms it will directly affect the fragmentation in AVX-512 it will actually provide a baseline unlike the mess AVX-512 is

511 · Oct 30, 2024

https://twitter.com/x/status/1851543622405026078

What is this new processor 😂

AcrosTinus · Oct 30, 2024

511 said:
I think it should be with M4 Max the power consumption is increasing though if i had to guess around 80W

You might be right, the good thing is that Apple has the P-Core to E-Core ratio right, Intel should copy that. Even on the smartphone side with Snapdragon 8 Elite, people are slowly moving towards Apple's core configs. They might be onto something, a indication for a 4P-6E Lunar Lake successor in the future.

AcrosTinus · Oct 30, 2024

511 said:
Widening of SIMD unit is undeniably going to happen to 512Bits AVX10 clears the fragmentation issues

Maybe, I think that AMD will cut down their SIMD on mainstream to 256bit as well. They are already introducing this restriction into mobile.

Kepler_L2 · Oct 30, 2024

511 said:
Widening of SIMD unit is undeniably going to happen to 512Bits AVX10 clears the fragmentation issues

No

naukkis said:
No, AVX10 just brings AVX512-instructions support to shorter registers without need to support 512 bits. So desktop-mobile could have AVX128 design.

Also no.

AVX10.2/128 is dead, Intel will continue with 512-bit implementation in servers and add 256-bit implementation in client.

tsamolotoff · Oct 30, 2024

511 said:
What is this new processor 😂

Netburst reborn, nice, maybe we'll live to see 10Ghz Tejas some day

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