Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

mzocyteae · Wednesday at 7:23 AM

Hulk said:
Based on the benches below it seems as though the L2 is where ARL is falling behind RPL, yes?

View attachment 110559

View attachment 110560

Those numbers don't make sense, and most likely a bugged benchmark.
If ARL L2 is that bad, its performance definitely should sunk much more.

According to RPL L2 numbers, this benchmark is measuring p-core (32B/c read @5.6G), excluding e-core.
While the ARL numbers are unclear yet, the LNL L2 numbers are known: p-core 32B/c; e-core ~27B/c.
With ARL p-core 5.4G/e-core 4.6G, this benchmark's numbers are way off (much lower than e-core) and looks broken.

511 · Wednesday at 7:56 AM

Kepler_L2 said:
No

Also no.

AVX10.2/128 is dead, Intel will continue with 512-bit implementation in servers and add 256-bit implementation in client.

Oh yes the community revolted on this CnC and Felix had a nice writeup for Killing AVX10/128 bit

GTracing · Wednesday at 8:36 AM

511 said:
Widening of SIMD unit is undeniably going to happen to 512Bits AVX10 clears the fragmentation issues

511 said:
Oh yes the community revolted on this CnC and Felix jad a nice writeup

I think your wording is causing some confusion. There's a difference between supporting 512bit instructions and having a 512bit wide pipeline. For example, Strix Point supports AVX512, but they do so through double-pumping a 256bit SIMD pipeline. I think most people agree that Intel and AMD will continue to use double pumping on client CPUs.

The point of Felix Leclair's article was that AVX10/128 should be dropped. And as Kepler said, AVX10/128 is dead. It was dropped in the AVX10.2 spec.

Hitman928 · Wednesday at 9:21 AM

poke01 said:
This doesn't make sense cause SPEC and R23 also showed that Arrow Lake made a generational increase over Raptor Lake.
Do we also disregard SPEC and R23 because these also failed to show regression in Arrow Lake?

IMO, these benchmarks should be taken as a guide and let real world productivity/gaming tests show the increases for your workflows.

Who did a Spec comparison for ARL? I haven’t seen it yet.

MS_AT · Wednesday at 9:28 AM

GTracing said:
I think your wording is causing some confusion. There's a difference between supporting 512bit instructions and having a 512bit wide pipeline. For example, Strix Point supports AVX512, but they do so through double-pumping a 256bit SIMD pipeline. I think most people agree that Intel and AMD will continue to use double pumping on client CPUs.

The point of Felix Leclair's article was that AVX10/128 should be dropped. And as Kepler said, AVX10/128 is dead. It was dropped in the AVX10.2 spec.

The leaks so far suggests that Intel will stick to AVX10/256 as efficient implementation of AVX10/512 with "double-pumping" would require full 512b shuffle units as shown by Zen4. That would not be doable if they want E-cores to keep using 128b execution units.

AMD hasn't yet announced anything about the AVX10 support, therefore we don't know if they will go Zen4/Zen5 mobile route [support 512b instructions but have 256b execution units], Zen 5 route [full 512b support] or Intel route [stick to 256b units].

Hitman928 said:
Who did a Spec comparison for ARL? I haven’t seen it yet.

David Huang has the scores for 265k on his blog SPEC(int) section, but he hasn't produced an article about Arrow Lake afaik.https://blog.hjc.im/spec-cpu-2017

deasd · Wednesday at 9:33 AM

Kepler_L2 said:
AVX10.2/128 is dead, Intel will continue with 512-bit implementation in servers and add 256-bit implementation in client.

This, is, big big disappointment if true. Unless Intel ditch big-little hybrid to have full 512bit support but it wouldn't happen until Intel combine big and little cores.

511 · Wednesday at 9:38 AM

GTracing said:
I think your wording is causing some confusion. There's a difference between supporting 512bit instructions and having a 512bit wide pipeline. For example, Strix Point supports AVX512, but they do so through double-pumping a 256bit SIMD pipeline. I think most people agree that Intel and AMD will continue to use double pumping on client CPUs.

Looks like it i was doing multiple things so i screwed it up

MS_AT · Wednesday at 10:00 AM

deasd said:
This, is, big big disappointment if true. Unless Intel ditch big-little hybrid to have full 512bit support but it wouldn't happen until Intel combine big and little cores.

Why disappointment? AVX10/256 doesn't mean you cannot use 128b, just that you have to support also 256b. This means if E-cores stay with 128b units, they will use the same trick Zen4 used for 512b compatibility, but targeting 256b compatibility. Nevertheless both cores will get other benefits like 32 architectural registers, masking and new instructions. This should be a noticeable boost, especially since spilling SIMD registers is expensive and it will also mean that Intel will reach ARM Neon parity in consumer market as Neon has had 32 architectural registers from the beginning.

dttprofessor · Wednesday at 10:01 AM

Granite rapids support avx 10.1

GTracing · Wednesday at 10:04 AM

511 said:
Looks like it i was doing multiple things so i screwed it up

No worries. I might have been a little aggressive with my response. I just get frustrated when people use vague language and argue over things that they actually might agree on.

MS_AT said:
The leaks so far suggests that Intel will stick to AVX10/256 as efficient implementation of AVX10/512 with "double-pumping" would require full 512b shuffle units as shown by Zen4. That would not be doable if they want E-cores to keep using 128b execution units.

AMD hasn't yet announced anything about the AVX10 support, therefore we don't know if they will go Zen4/Zen5 mobile route [support 512b instructions but have 256b execution units], Zen 5 route [full 512b support] or Intel route [stick to 256b units].

Thanks for the correction. I guess I meant to say that they aren't necessarily moving to 512bit wide SIMD execution pipelines.

deasd said:
This, is, big big disappointment if true. Unless Intel ditch big-little hybrid to have full 512bit support but it wouldn't happen until Intel combine big and little cores.

Intel could also add AVX10/256 support to the little cores.

Here's the only source I could find on it. But the tweet is from the same guy who wrote the Chips and Cheese article. Sounds like it's actually AVX10.3 that drops 128, not AVX10.2, so I got that wrong.

https://www.reddit.com/r/hardware/comments/1ehhrys/intel_unveils_avx10_revision_30_128bit_only

DrMrLordX · Wednesday at 10:10 AM

GTracing said:
Intel could also add AVX10/256 support to the little cores.

Pretty sure even Goldmont/Goldmont+ could run 256b AVX2 code! It was dog slow but it worked.

João Bortolace · Wednesday at 10:29 AM

DrMrLordX said:
Pretty sure even Goldmont/Goldmont+ could run 256b AVX2 code! It was dog slow but it worked.

AVX was not added to gracemont?

511 · Wednesday at 10:38 AM

João Bortolace said:
AVX was not added to gracemont?

they only have 2*128bit SIMD on gracemont and it is doublepumped FP improvements are massive in Skymont due to a weak baseline in Gracemont

511 · Wednesday at 11:08 AM

M4 Pro is 1600 r24 ( from slides)(45-50W based on M3)
M2 Pro is 1000
U9 185(1000 at 65W) iirc
Strix is 1250(65W)

igor_kavinski · Wednesday at 11:25 AM

DrMrLordX said:
Pretty sure even Goldmont/Goldmont+ could run 256b AVX2 code! It was dog slow but it worked.

Can't find any mention of AVX here: https://en.wikipedia.org/wiki/Goldmont_Plus

Kosusko · Wednesday at 12:47 PM

Intel's Arrow Lake chips aren't winning any awards for gaming performance but I think its new E-cores deserve a gold star

source: https://www.pcgamer.com/hardware/pr...t-i-think-its-new-e-cores-deserve-a-gold-star

P.S. Paradigm shift: 12c .LITTLE Atom Skymont E-cores beats 8C big Lion Cove P-cores !
source:

Page 10 - Question - Intel Mont thread

Page 10 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

511 · Wednesday at 1:00 PM

40 Core M4 Max GPU vs 8 Xe2 Core iGPU

TESKATLIPOKA · Wednesday at 1:08 PM

511 said:
40 Core M4 Max GPU vs 8 Xe2 Core iGPU
View attachment 110592

GPU performance in what? Doesn't looks like It's in a game.

511 · Wednesday at 1:24 PM

TESKATLIPOKA said:
GPU performance in what? Doesn't looks like It's in a game.

Don't ask me i don't make apple slides they didn't mention anywhere what did they test.I am pretty sure that LNL and M4 GPU are within 10% of each other.
They also claim M4 Pro 20 Core gpu is 2X faster than M4 GPU(10 Core Version) additionally it has 2X bandwidth it would be half

It’s up to 2.2x faster than the CPU in M1 Max and up to 2.5x faster than the latest AI PC chip. M4 Max

The GPU features up to 20 cores for graphics performance that is 2x that of M4, and up to 2.4x faster than the latest AI PC chip M4 Pro

Apparently 2.4X of 258V and 2X for M4 apparently U9 is 5% faster so M4 iGPU is roughly 15% faster CPU being 150% faster

Hitman928 · Wednesday at 1:36 PM

MS_AT said:
The leaks so far suggests that Intel will stick to AVX10/256 as efficient implementation of AVX10/512 with "double-pumping" would require full 512b shuffle units as shown by Zen4. That would not be doable if they want E-cores to keep using 128b execution units.

AMD hasn't yet announced anything about the AVX10 support, therefore we don't know if they will go Zen4/Zen5 mobile route [support 512b instructions but have 256b execution units], Zen 5 route [full 512b support] or Intel route [stick to 256b units].

David Huang has the scores for 265k on his blog SPEC(int) section, but he hasn't produced an article about Arrow Lake afaik.https://blog.hjc.im/spec-cpu-2017

Thanks, I don’t see any real increase from RPL to ARL in that test. The 265k is slightly behind in raw score and ~2% ahead in IPC.

Edit: Updated IPC comment as I used the wrong freq. initially to compare.

Doug S · Wednesday at 1:59 PM

TESKATLIPOKA said:
GPU performance in what? Doesn't looks like It's in a game.

Apple has said previously they do such comparison testing across a range of applications that are commonly run by their customers. So you can assume they aren't testing on leading AAA games.

eek2121 · Wednesday at 2:05 PM

sgs_x86 said:
Follow up to ADL-N is a refresh of ADL-N called Twin Lake. There is no E-core only cpu based on Skymont.

Twin Lake is just that. Skymont cores.

DZero · Wednesday at 2:48 PM

eek2121 said:
Twin Lake is just that. Skymont cores.

If that so... heck, Conroe jump all over again?

DavidC1 · Wednesday at 2:49 PM

João Bortolace said:
AVX was not added to gracemont?

Gracemont has AVX2 support. It supports FMA which is part of AVX2's specification but it's 128-bit units so it has to be done over 2 cycles.

511 · Wednesday at 2:52 PM

DavidC1 said:
Gracemont has AVX2 support. It supports FMA which is part of AVX2's specification but it's 128-bit units so it has to be done over 2 cycles.

Same with skymont it also has only 128 bit units

Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Senior member

Attachments

Junior Member

Senior member

Member

Diamond Member

Senior member

Senior member

Senior member

Senior member

Member

Member

Lifer

Member

Senior member

Senior member

Attachments

Lifer

Member

Intel's Arrow Lake chips aren't winning any awards for gaming performance but I think its new E-cores deserve a gold star​

Senior member

Platinum Member

Senior member

Diamond Member

Platinum Member

Diamond Member

Member

Golden Member

Senior member

Intel's Arrow Lake chips aren't winning any awards for gaming performance but I think its new E-cores deserve a gold star