Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

DrMrLordX · 2024-10-31T00:16:30-0400

igor_kavinski said:
Can't find any mention of AVX here: https://en.wikipedia.org/wiki/Goldmont_Plus

Atom cores have supported 2*128b AVX2 for quite some time. I used to have access to a Pentium J quad core and even ran some crap like y-cruncher on it. AVX2 performance was atrociously poor, but it did work.

511 · 2024-10-31T00:39:35-0400

We need another Andy Grove to save the company who had different mindset.

i remember talking to a guy in a thread when intel were moving from Memory to CPU,he personally went to the chief of a factory and fired him cause he didn't agree to his plans. He simply fired people on the spot if they didn't do their jobs properly

Rheingold · 2024-10-31T00:53:04-0400

Kocicak said:
illustrated how useless HT is

Very good work, but this part misses the plot. Averaging the HT benefit across active threads doesn't make much sense. In reality, almost all situations that benefit from HT will be all-core loads. So, ARL could have had up to 13.5% more multi-core performance.

Going from statements for earlier implementations of HT, it adds around 5% to the core size. With 4.53 mm² for Lion Cove, that's just +1.812 mm² for 8 P-cores. or a bit more than one Skymont E-core. The Compute tile would have been just 1.6% bigger, for up to 13.5% more performance. Performance-wise, that should still have been a no-brainer.

The reasons could be in unified core architecture across Lunar and Arrow Lake, and in preparation for unifying P- and E-cores in upcoming generations.

Doug S · 2024-10-31T02:01:37-0400

itsmydamnation said:
Dumb take....

Like every pure play design company would not exist by that logic. Or there would just a different pure play foundry instead , maybe Samsung, maybe TI etc and things would roughly be the same.

OK so instead of "if it wasn't for TSMC" maybe he should have said "if it wasn't for TSMC's success after success in delivering on new nodes". Because yeah if they had used Samsung they would have been screwed especially the last few years. Sure they might have had some good CPU designs but they'd arrive late and suffer from low volume production that couldn't come remotely close to meeting demand.

DavidC1 · 2024-10-31T02:05:37-0400

Rheingold said:
Going from statements for earlier implementations of HT, it adds around 5% to the core size.

That's only true for physical area and transistor count. Because of the need for extra validation, it adds something material in a negative way - worse execution.

Inside Nehalem: Intel's Future Processor and System

Learn the details on Intel's 45nm Nehalem processor, which features an new system interface: DDR3 integrated memory controllers and CSI or QuickPath Interconnects. The Penryn/Core microarchitecture has been substantially upgraded with improvements spanning the whole pipeline, especially notable...

www.realworldtech.com

A much more plausible explanation is that while designing a SMT processor is relatively easy – the validation is extremely difficult. Supposedly Willamette, the 180nm P4, actually had all the necessary circuitry for SMT present, but it was disabled due to the difficulty of validating SMT until the tail end of the Northwood 130nm generation. More importantly, almost all of the experience with designing, validating and debugging SMT processors resides with Intel’s Hillsboro design team, rather than the group in Haifa. Thus a decision to avoid SMT for the Core 2 makes a lot of sense from a risk management perspective.

This is why I would not be surprised at all a Unified Core led by the current E core chief architect, Stephen Robinson will take out BOTH the uop cache and SMT. In fact, I'm expecting it.

If the increased difficult of validation adds 5%, then that is something that could be used to reduce TTM and reduce risk, for the entire CPU, every generation, possibly compounding over time.

Apple M4 might do 1800 in R24 at 60W. Blowout performance per watt. It doesn't have SMT. Just a stellar good architecture.

DrMrLordX said:
DrMrLordX said:

Atom cores have supported 2*128b AVX2 for quite some time. I used to have access to a Pentium J quad core and even ran some crap like y-cruncher on it. AVX2 performance was atrociously poor, but it did work.

Click to expand...

That's the point of a CPU. If it doesn't have explicit support, it runs on software, on the general purpose pipeline.

AVX2 adds FMA support over AVX, which doesn't happen until Gracemont.

Kocicak · 2024-10-31T04:03:04-0400

biostud said:
Apperently it is a hard sell in EU

You first need to have some CPUs to sell. The only commonly available CPU at some retailers was 265K, and it has been selling.

511 · 2024-10-31T04:06:23-0400

265K is actually a good processor to buy vs 285K 4E cores for >100$ lmao if you want to get Z890

Kocicak · 2024-10-31T04:06:30-0400

Rheingold said:
Very good work, but this part misses the plot. Averaging the HT benefit across active threads doesn't make much sense. In reality, almost all situations that benefit from HT will be all-core loads. So, ARL could have had up to 13.5% more multi-core performance.

That is a theoretical maximal benefit, I am convinced that the real MT apps would see significantly lower benefit.

Det0x · 2024-10-31T05:07:52-0400

Intel gets downgraded to a "lower tier customer" by TSMC

Intel CEO Lost A 40% Discount For TSMC's Latest Chip Tech After Taiwan Remarks - Report

Intel CEO Patrick Gelsinger's remarks about TSMC's Taiwan risk jeopardized a hefty discount that TSMC had offered the firm, says report.

wccftech.com

And ADATA gets downgraded to a "lower tier customer" by Intel

https://videocardz.com/newz/intel-reportedly-drops-adata-from-tier1-ddr5-memory-supplier-list-for-arrow-lake-over-cudimm-deployment-remarks

In business relations it better to keep quiet than criticize your partners it seem 🤷‍♀️ 😅

SiliconFly · 2024-10-31T05:51:34-0400

igor_kavinski said:
Another example of Pat digging Intel's grave!

BS. Now that 18A has powered up and is getting ready to compete, we can expect more nonsense like this from TSMC. They're just attacking the weakest link in the chain.

511 · 2024-10-31T06:00:18-0400

Det0x said:
Intel gets downgraded to a "lower tier customer" by TSMC

Intel CEO Lost A 40% Discount For TSMC's Latest Chip Tech After Taiwan Remarks - Report

Intel CEO Patrick Gelsinger's remarks about TSMC's Taiwan risk jeopardized a hefty discount that TSMC had offered the firm, says report.

wccftech.com

I don't doubt it happened but 40% that is huge i don't think the discount was that much i am pretty sure they got their discount removed but 40% you know TSMC has 50%+ Margin why would they give Intel Such a big discount?

The articles at returns has truth with Made up numbers we will have a investor call today we will know

coercitiv · 2024-10-31T06:35:54-0400

511 said:
I don't doubt it happened but 40% that is huge i don't think the discount was that much i am pretty sure they got their discount removed but 40% you know TSMC has 50%+ Margin why would they give Intel Such a big discount?

People focus on their idea of what this discount means, I suggest we focus on the events we know so far:

Intel did make very dangerous public statements about TSMC
Pat Gelsinger was forced to go in Taiwan soon after to repair / renegotiate a deal, and also publicly did a 180 degree spin with regards to TSMC.

Something nasty obviously happened, it was not just a minor snag. We obviously know a contract would not allow random price changes, but we also don't know if the discount was related to their initial allotment or maybe further orders, or part of the orders etc. TSMC may also have included wording in their contract that prevented Intel from publicly disparaging them.

I think it's safe to say Intel did pay for their behavior, in dollars. I also think they did not have to pay 60%+ for the wafers already under contract.

Nothingness · 2024-10-31T08:20:34-0400

Hulk said:
How did Intel get here?

Complacency and corporate culture.

511 · 2024-10-31T08:23:52-0400

Nothingness said:
Complacency and corporate culture.

Add the CEOs to the list that started it from Paul to Swan let's see what Pat does until he is let go

Nothingness · 2024-10-31T08:26:25-0400

511 said:
Add the CEOs to the list that started it from Paul to Swan let's see what Pat does until he is let go

I count that as corporate culture

Hulk · 2024-10-31T08:52:15-0400

ARL is a stumble of sorts. The question is if it is a stumble on the way down or the way up. I wonder if there is a sense of excitement at Intel, young and old really smart people passionate to do great things on the edge of current technology? Or it is just full of people grinding away and feeling like cogs in a machine that doesn't care about them with a room full of executives figuring out how to get the remaining gold off of the ship before it sinks?

511 · 2024-10-31T08:53:27-0400

Hulk said:
ARL is a stumble of sorts. The question is if it is a stumble on the way down or the way up. I wonder if there is a sense of excitement at Intel, young and old really smart people passionate to do great things on the edge of current technology? Or it is just full of people grinding away and feeling like cogs in a machine that doesn't care about them with a room full of executives figuring out how to get the remaining gold off of the ship before it sinks?

That is something only a Employee at Intel Knows but the Executive Rot is so real

igor_kavinski · 2024-10-31T08:56:00-0400

511 said:
let's see what Pat does until he is let go

They are gonna have trouble finding a CEO who is willing to dance on stage

Ballmer might be interested!

cannedlake240 · 2024-10-31T09:01:37-0400

Hulk said:
ARL is a stumble of sorts. The question is if it is a stumble on the way down or the way up. I wonder if there is a sense of excitement at Intel, young and old really smart people passionate to do great things on the edge of current technology? Or it is just full of people grinding away and feeling like cogs in a machine that doesn't care about them with a room full of executives figuring out how to get the remaining gold off of the ship before it sinks?

Morale is probably very low across the company. If 18A is looking alright maybe there's excitement in Process TD groups and fabs

igor_kavinski said:
They are gonna have trouble finding a CEO who is willing to dance on stage

Ballmer might be interested!

If it gets to that Intel will be acquired or large parts will be sold off

DAPUNISHER · 2024-10-31T09:06:13-0400

511 said:
That is something only a Employee at Intel Knows but the Executive Rot is so real

The Intel employees on reddit talk about all of the experienced and talented taking the buyouts or going through the motions while they actively look for work elsewhere. Rock bottom morale. How the pay was not competitive when they took the job, but the perks (most of which have been taken away) were what made it worth working there.

A few that thought they were safe because they work at the Hillsboro campus. They were unfortunately quite wrong. That was 4-8 weeks ago I read those posts on r/Intel, r/hardware, and maybe one or 2 other subs.

igor_kavinski · 2024-10-31T09:06:29-0400

cannedlake240 said:
If 18A is looking alright maybe there's excitement in Process TD groups and fabs

Hope they release Arrow Lake with bugs fixed on 18A in six months and max boost 6 GHz to get consumer and investor confidence back. They can just increment the model numbers by 5 like 250K, 270K and 290K.

gaav87 · 2024-10-31T09:07:25-0400

Enjoy my find guys Battlemage with 288EU and 320EU

OneEng2 · 2024-10-31T09:07:42-0400

igor_kavinski said:
I think Arrow Lake shows why CB2024 should never ever be taken seriously as a benchmark ever again. And to an extent, Geekbench too. Scores of both failed to predict serious regression inducing issues/bugs in ARL's design.

I don't know about not being taken seriously; however, it really shows that these benchmarks do not utilize the processor in a very representative way and that real world benchmarks in real world conditions will always be the gold standard, not some "all-in-one" benchmark.

In fact, as CPU products become more and more specialized with the use of tiles and mixes of different types of cores, it will become more and more important for real-world benchmarks to be run so that people can gauge what product is best for what they do most often with their computer.

Magio said:
Funny they're comparing their 80W (based on M3 Max) chip which starts at over 4000€ here with LNL. 😂

... and there is the elephant in Apple's room that I haven't seen anyone point out before. I haven't looked up the figures, but I am going out on a limb here and saying that I bet there are 50 x86 laptops sold for every Mac Book.

gdansk said:
32nm Sandy Bridge vs 32nm Bulldozer.
22nm Ivy Bridge vs 32nm Piledriver.

Later still, in 2015, it was:
14nm Skylake vs 32nm Piledriver and 28nm Excavator.

Yes, but I believe that the devil is also in the details. IIRC, back in those days, even on what was called the same process node, Intel was achieving much better density and power per area metrics than AMD, so it was actually much worse than it looked at a casual glance.

igor_kavinski · 2024-10-31T09:09:23-0400

gaav87 said:
Enjoy my find guys Battlemage with 288EU and 320EU

View attachment 110665

Is the 320EU part gonna be for workstations?

gaav87 · 2024-10-31T09:11:08-0400

igor_kavinski said:
Is the 320EU part gonna be for workstations?

Im 99% sure the shipping guys, made an error and its 160EU 20xe2 cores.
If not it means its 40xe2 cores and that's HUGE ~4080s perf

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