Aaaaannd we're back to +40% for Zen5. On server looks like the new SKUs did gain about 40% with the same number of cores.
The consistent ~1.4x uplift from the EPYC 9654 to EPYC 9655 was all the more impressive when finding that the average CPU power use only increased by about ~5% on average and only an 11% increase to the default/peak TDP.
Yeah I wasn't like lying or something. Just no idea how it translated to badly to client parts even in raw nT zoomzooms.Aaaaannd we're back to +40% for Zen5
Spoiler alert: ... the clocks statement was about the CCD without the cache die.Uh wow, based on statements made by AMD per GN, the 9950X3D might have similar clocks to the vanilla part. The cache wasn’t the limit, the cores were because of lack of cooling. Cache is now under the cores, so no more limit.
Considering what we got from the leaker and the strong hints for 2x X3D dies, I still think the most probable outcome isSpoiler alert: ... the clocks statement was about the CCD without the cache die.
Wouldn't be the first time people misread too much into statement that were meant to say something else.
Very interesting info about the stacking changes on the new X3D chips:
Phew.Yeah I wasn't like lying or something. Just no idea how it translated to badly to client parts even in raw nT zoomzooms.
Tech Nostradamus strikes again.Hmm, so based on discussions between AMD and GN, 5.4Ghz OC is within reach for a good chunk of the chips, lottery rules will obviously apply.
Well at least we do know now how it happened. Some PPC gains combined with massively better v/f curve in the 2-4 GHz region allowing Turin to maintain higher clocks/boost higher than the predecessor, it's just that it's irrelevant at the very top end of it where the client parts live.Yeah I wasn't like lying or something. Just no idea how it translated to badly to client parts even in raw nT zoomzooms.
And many people repeatedly warned that one should not extrapolate from Turin. But the hypers did anyway.Well at least we do know now how it happened. Some PPC gains combined with massively better v/f curve in the 2-4 GHz region allowing Turin to maintain higher clocks/boost higher than the predecessor, it's just that it's irrelevant at the very top end of it where the client parts live.
Entirely correct.And many people repeatedly warned that one should not extrapolate from Turin. But the hypers did anyway.
Better, some F SKUs are 5G allcore. It's nifty.Some PPC gains combined with massively better v/f curve in the 2-4 GHz region allowing Turin to maintain higher clocks/boost higher than the predecessor, it's just that it's irrelevant at the very top end of it where the client parts live.
On the same-ish node no less.Not the most obvious thing for a massively wider core to clock higher at the same power admittedly.
You see what Intel did with N3B, they butchered it.On the same-ish node no less.
LNL is fine. ARL-S is indeed a waste of N3b wafers.You see what Intel did with N3B, they butchered it.
AMD does ship an N3e product too, it's Turin-D. And it's class-leading.AMD did a more than a fine job.
And what of ARL-H?LNL is fine. ARL-S is indeed a waste of N3b wafers.
It exists.And what of ARL-H?
At 50W cinememe hopefully.I still think it'll be better than Strix Point
Where?the strong hints for 2x X3D dies
Nobody is talking about a process shrink. N4P is still made on the 5nm process. Going from N5 to N4P is a big generational jump in both performance and efficiency. If the 9800x3D is only 7-8% better than the 7800x3D. That would fall outside (11% performance increase) if AMD made a 7800x3D on N4P. There is a difference between real world and paper statistics. At the same time, TSMC cannot publish performance and power efficiency numbers that are not accurate. Customers would not buy their silicon if the numbers were not accurate.Yes, TSMC's performance statements aren't regarding designs already at the very edge of their process. Shrink a 5GHz design and you are not getting 5.5GHz. If you look into it TSMC are comparing a ~3GHz test chip.
But it won't stop Hans "It's all process" Gruber.
Where?
Nobody is talking about a process shrink. N4P is still made on the 5nm process. Going from N5 to N4P is a big generational jump in both performance and efficiency. If the 9800x3D is only 7-8% better than the 7800x3D. That would fall outside (11% performance increase) if AMD made a 7800x3D on N4P. There is a difference between real world and paper statistics. At the same time, TSMC cannot publish performance and power efficiency numbers that are not accurate. Customers would not buy their silicon if the numbers were not accurate.
Forum members should stop reading reviews or watching youtube vidoes on how silicon process works. You either get efficiency or performance increase, not both is BS. It depends on the node and the variant TSMC offers. The N3 3nm silicon only gives a significant efficiency increase over 5nm. There are clock regressions with N3 and no performance uplift. You cannot choose I want performance over efficiency. You have to wait for a N3P to get performance and efficiency gains. When they say it's customized for AMD. That simply means they give them an option to lean towards power or efficiency or a mix of both depending on the process.
When AMD was set to use N3 with Zen 5 they mentioned clock regressions and suddenly that changed when they had to use N4P. No clock regressions but clock increases. People attribute increased clocks to the Zen 5 design. I attribute it to N4P. Zen 4 was originally supposed to be on N5P but they could not get N5P. They settled for the base N5 silicon. A 7800x3D on N4P would yield very good efficiency and performance gains based on the N4P silicon.
Sometimes core density matters more than anything. Take Nvidia's Blackwell. That chip is so advanced they really needed to be on TSMC 3nm but Apple bought all the N3 silicon. Instead, Blackwell is on N4P which provides increased silicon density over all other 5nm processes.