Possibly so. As I have said, Arrow Lake appears to be a very good laptop chip.And what of ARL-H?
I still think it'll be better than Strix Point.
When TSMC says "performance" it isn't referring to benchmarks, and it is qualified as to what it does mean.Nobody is talking about a process shrink. N4P is still made on the 5nm process. Going from N5 to N4P is a big generational jump in both performance and efficiency. If the 9800x3D is only 7-8% better than the 7800x3D. That would fall outside (11% performance increase) if AMD made a 7800x3D on N4P. There is a difference between real world and paper statistics. At the same time, TSMC cannot publish performance and power efficiency numbers that are not accurate. Customers would not buy their silicon if the numbers were not accurate.
Forum members should stop reading reviews or watching youtube vidoes on how silicon process works. You either get efficiency or performance increase, not both is BS. It depends on the node and the variant TSMC offers. The N3 3nm silicon only gives a significant efficiency increase over 5nm. There are clock regressions with N3 and no performance uplift. You cannot choose I want performance over efficiency. You have to wait for a N3P to get performance and efficiency gains. When they say it's customized for AMD. That simply means they give them an option to lean towards power or efficiency or a mix of both depending on the process.
When AMD was set to use N3 with Zen 5 they mentioned clock regressions and suddenly that changed when they had to use N4P. No clock regressions but clock increases. People attribute increased clocks to the Zen 5 design. I attribute it to N4P. Zen 4 was originally supposed to be on N5P but they could not get N5P. They settled for the base N5 silicon. A 7800x3D on N4P would yield very good efficiency and performance gains based on the N4P silicon.
Sometimes core density matters more than anything. Take Nvidia's Blackwell. That chip is so advanced they really needed to be on TSMC 3nm but Apple bought all the N3 silicon. Instead, Blackwell is on N4P which provides increased silicon density over all other 5nm processes.
I don't know. Maybe watch all the Hardware Unboxed Zen 5 reviews and get back to me.Possibly so. As I have said, Arrow Lake appears to be a very good laptop chip.
When TSMC says "performance" it isn't referring to benchmarks, and it is qualified as to what it does mean.
Your assertion that Zen 4 would perform the same as Zen 5 on the same process node is nonsensical. You surely see that, right?
I can plug Phoronix in return. Don't be a lolcow.Maybe watch all the Hardware Unboxed Zen 5 reviews and get back to me.
especially when my next GFX card is expected to cost over 2 grands (5090)
It didn't.Supposedly Zen2 already had TSVs that never got used
MI300 kinda is already? tons of shoreline I/O and d2d there.Maybe stacked logic is going to finally become a thing?
Not even remotely the same concept as stacked logic.MI300 kinda is already? tons of shoreline I/O and d2d there.
So any rumors about dual stacked CCDs? Or was all the news about TSVs being on top of the die just people getting their analysis wrong?
Supposedly Zen2 already had TSVs that never got used, maybe a Zen5+ or Zen6 will have fully sandwiched dies? Maybe stacked logic is going to finally become a thing?
I'm still skeptical about them finding a way to join the two CCDs together on a single interposer without changing the IOD, let alone that being economical, but maybe thats what the top side vias are for?
High Yield made a video about it, and there was another twitter tech poster (I can't remember) that did another zen 5 die analysis. All from the Fritzchens Fritz pictures. Pretty sure I found both of those from this thread.No stacked logic. Not sure what you mean by TSVs being on top of the die.
High Yield made a video about it, and there was another twitter tech poster (I can't remember) that did another zen 5 die analysis. All from the Fritzchens Fritz pictures. Pretty sure I found both of those from this thread.
So either these people were just making things up, or there would be something else going on with multiple stacks of silicon.
As far as I am aware, Fritzchens Fritz has never taken a picture that wasn't a top down view.I don’t remember them claiming TSVs on the top of the die. Did you mean TSVs on the top die?
Thats wrong my friend. For tsmc 'performance' increase is BASE clock speed increase at 1.2V. Not benchmark perf +x% !!Nobody is talking about a process shrink. N4P is still made on the 5nm process. Going from N5 to N4P is a big generational jump in both performance and efficiency. If the 9800x3D is only 7-8% better than the 7800x3D. That would fall outside (11% performance increase) if AMD made a 7800x3D on N4P. There is a difference between real world and paper statistics. At the same time, TSMC cannot publish performance and power efficiency numbers that are not accurate. Customers would not buy their silicon if the numbers were not accurate.
Forum members should stop reading reviews or watching youtube vidoes on how silicon process works. You either get efficiency or performance increase, not both is BS. It depends on the node and the variant TSMC offers. The N3 3nm silicon only gives a significant efficiency increase over 5nm. There are clock regressions with N3 and no performance uplift. You cannot choose I want performance over efficiency. You have to wait for a N3P to get performance and efficiency gains. When they say it's customized for AMD. That simply means they give them an option to lean towards power or efficiency or a mix of both depending on the process.
When AMD was set to use N3 with Zen 5 they mentioned clock regressions and suddenly that changed when they had to use N4P. No clock regressions but clock increases. People attribute increased clocks to the Zen 5 design. I attribute it to N4P. Zen 4 was originally supposed to be on N5P but they could not get N5P. They settled for the base N5 silicon. A 7800x3D on N4P would yield very good efficiency and performance gains based on the N4P silicon.
Sometimes core density matters more than anything. Take Nvidia's Blackwell. That chip is so advanced they really needed to be on TSMC 3nm but Apple bought all the N3 silicon. Instead, Blackwell is on N4P which provides increased silicon density over all other 5nm processes.
Not even directly applicable given the amount of DTCO involved in this day and age.For tsmc 'performance' increase is BASE clock speed increase at 1.2V.
That's wrong. If you run two identical processors on different processes on the 5nm node. Clock for clock the performance on N4P will be 11% better on average than on N5. That means if you run a 7800x3d @ 1.2v and 4ghz. The N4P at the same clock and voltage would perform 11% better than on N5 with identical clocks and voltage. The efficiency gains means at the same voltage it would take eg. 10% less power to produce the same result. The increased clocks are primarily due to silicon and or voltage.Thats wrong my friend. For tsmc 'performance' increase is BASE clock speed increase at 1.2V. Not benchmark perf +x% !!
Boost clock has nothing to do with it except where they clearly specify Fmax increase. Boost clock depends on many factors but cba educating. So in other words +11% for your imaginary node jump for 7800x3d would increase base clock speed by 11% not the boost clock. Boost clock could still be the same.
Fun fact. AMD actually wanted the Zen 4 CPU's on N5P but they had to settle for N5.
Dr Su reinforced that technology roadmaps are all about making the right choices and the right junctures, and explicitly stated that our 5nm technology is highly optimized for high-performance computing – it’s not necessarily the same as some other 5nm technologies out there
One link in your chain of errors is your interpretation that anybody claimed that 9800X3D was 8% faster than 7800X3D. AMD at least did not say that. Here is AMD's claim in their October 31 press release:If the 9800x3D is only 7-8% better than the 7800x3D [...]
Seek help.That's wrong. If you run two identical processors on different processes on the 5nm node. Clock for clock the performance on N4P will be 11% better on average than on N5. That means if you run a 7800x3d @ 1.2v and 4ghz. The N4P at the same clock and voltage would perform 11% better than on N5 with identical clocks and voltage. The efficiency gains means at the same voltage it would take eg. 10% less power to produce the same result. The increased clocks are primarily due to silicon and or voltage.
Aaaaannd we're back to +40% for Zen5. On server looks like the new SKUs did gain about 40% with the same number of cores.
No. That doesnt make any sense at all. If you run Proc A at 4 GHz and then you run Proc A on a newer, superior node, but identical design and logic, it will perform exactly the same at the same frequency with better efficiency.That's wrong. If you run two identical processors on different processes on the 5nm node. Clock for clock the performance on N4P will be 11% better on average than on N5. That means if you run a 7800x3d @ 1.2v and 4ghz. The N4P at the same clock and voltage would perform 11% better than on N5 with identical clocks and voltage.
That's really going to depend on what was limiting Fmax on that logic. If it was power limited or thermal limited, then, no, you CAN get SOME limited frequency improvement.No. That doesnt make any sense at all. If you run Proc A at 4 GHz and then you run Proc A on a newer, superior node, but identical design and logic, it will perform exactly the same with better efficiency.
The non-bold parts are only true for the exact conditions and mix of logic that TSMC quotes the metrics for.That's wrong. If you run two identical processors on different processes on the 5nm node. Clock for clock the performance on N4P will be 11% better on average than on N5. That means if you run a 7800x3d @ 1.2v and 4ghz. The N4P at the same clock and voltage would perform 11% better than on N5 with identical clocks and voltage. The efficiency gains means at the same voltage it would take eg. 10% less power to produce the same result. The increased clocks are primarily due to silicon and or voltage.
I would almost bet money on 5.5ghz+ for the 9950X3D. I would absolutely not be shocked if the chip hit 5.7ghz, but 5.5 is plenty. The 9900X3D will be slightly lower.Considering what we got from the leaker and the strong hints for 2x X3D dies, I still think the most probable outcome is
5.3 Ghz boost clock for the 9900X3D
5.4 Ghz boost clock for the 9950X3D
Two dies would also make 9900X3D an actually viable product (in gaming)
As far as I am aware, Fritzchens Fritz has never taken a picture that wasn't a top down view.
AMD put out a video today that showed the cache being under the die... so what else could I mean eh? Surely you're not getting into semantics about the position of flip chips right?
I honestly am not sure what you meant so I guess I'll answer the question as asked, no, no one thought the TSVs were on the top of the CCD die.
Zen 5 die: TSV's to the 64 MB X3D L3 cache:
It simply must have enough and well distributed TSV's...
It looks like a all the TSV's providing the power to the X3D L3 die are using an MIM decoupling capacitor for each power and ground pair of TSV's leading to something like an extra ~8500 power/ground TSV's. Under each black square should be two TSV's.
Original die photos: https://www.flickr.com/photos/130561288@N04/
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