Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

Hulk · Nov 1, 2024

It is getting hard for me to take Intel process timelines seriously because they seem to miss their deadlines so regularly. ARL disappoints architecturally and isn't on Intel 20A. Might be time for an AMD/Intel pair trade.

It just seems like IPC-wise x86 is nearly topped out. Zen 5 didn't show big gains and Lion Cove showed gains and regression. It seems more likely that the E cores will approach current ST iso frequency performance and peter out as well at that performance level as well, they just end up at that performance level in a more area efficient manner.

Without software help like new instructions or something I don't see how we get another 15 to 20% increase on a generation from either Zen 5 or LNC? 8 wide is already too wide, right?

On that same note, considering performance regression is LNC still +9% over Raptor Cove?

511 · Nov 1, 2024

Hulk said:
It is getting hard for me to take Intel process timelines seriously because they seem to miss their deadlines so regularly. ARL disappoints architecturally and isn't on Intel 20A. Might be time for an AMD/Intel pair trade.

It just seems like IPC-wise x86 is nearly topped out. Zen 5 didn't show big gains and Lion Cove showed gains and regression. It seems more likely that the E cores will approach current ST iso frequency performance and peter out as well at that performance level as well, they just end up at that performance level in a more area efficient manner.

Without software help like new instructions or something I don't see how we get another 15 to 20% increase on a generation from either Zen 5 or LNC? 8 wide is already too wide, right?

On that same note, considering performance regression is LNC still +9% over Raptor Cove?

The performance regression is due to L3 and mix of other Factors LNC is not a big upgrade either it's just Meh.
If it was same performance at half the power without regression it would have been good but it is a mixed bag a 3-5% gaming regression would have been swallowable with these uplift I don't see U9 285K as a good value outside overclockers and Platform Features like tons of NVMe and IO

reaperrr3 · Nov 1, 2024

Hulk said:
It just seems like IPC-wise x86 is nearly topped out. Zen 5 didn't show big gains and Lion Cove showed gains and regression.

Zen5 was a ground-up redesign of the pipeline, lost some of Zen4's optimizations, focused more on DC workloads than desktop, is still 4-wide per decoder/thread, and rumored to have gone through multiple design team switches and a generally hiccup-ridden development.

Also, most significant IPC increases in the past for games came alongside significant cache size/topology bumps (Zen2: doubled L3 per core, Zen3: doubled cores per CCX->up to 2x L3 per core/thread, Zen4: doubled L2, ADL: massive cache bump over CFL/ICL), of which Zen5 has virtually none.

And LNC in ARL looks like either their chiplet technology is still inferior to AMD's and holding back the cores, or they just borked the core's design somewhere. Not sure you should take ARL as example for IPC headroom petering out.

mikk · Nov 1, 2024

Maybe we can expect a 5% bump from Darkmont over Skymont, there are some changes.

https://twitter.com/x/status/1852244184696021423

https://twitter.com/x/status/1852285701951307808

The E core team can do this with some tweaks here and there (like Crestmont). The Cove team usually needs big changes for the same performance increase. We don't know about Cougar Cove though. Maybe they can fix some things over Lion Cove.

Hulk · Nov 1, 2024

reaperrr3 said:
Zen5 was a ground-up redesign of the pipeline, lost some of Zen4's optimizations, focused more on DC workloads than desktop, is still 4-wide per decoder/thread, and rumored to have gone through multiple design team switches and a generally hiccup-ridden development.

Also, most significant IPC increases in the past for games came alongside significant cache size/topology bumps (Zen2: doubled L3 per core, Zen3: doubled cores per CCX->up to 2x L3 per core/thread, Zen4: doubled L2, ADL: massive cache bump over CFL/ICL), of which Zen5 has virtually none.

And LNC in ARL looks like either their chiplet technology is still inferior to AMD's and holding back the cores, or they just borked the core's design somewhere. Not sure you should take ARL as example for IPC headroom petering out.

Okay. What is the IPC gain overall for LNC and Zen 5?

511 · Nov 1, 2024

mikk said:
Maybe we can expect a 5% bump from Darkmont over Skymont, there are some changes.

https://twitter.com/x/status/1852244184696021423

https://twitter.com/x/status/1852285701951307808

The E core team can do this with some tweaks here and there (like Crestmont). The Cove team usually needs big changes for the same performance increase. We don't know about Cougar Cove though. Maybe they can fix some things over Lion Cove.

You know his tweets are protected lol but those are major changes
Instructions decode 20B-> 24B increase in per cycle bandwidth
Two Taken Conditional branch
L2 cache improvement
It will be a Gracemont -> Crestmont Jump 3-7% IPC considering the small core is RPC IPC so higher IPC than a 5th gen Xeon core outside of AVX-512 🤣 and consuming way less power i hope Clearwater Forest is actually good with these

DavidC1 · Nov 1, 2024

Magio said:
Just to be sure, is 20% speculation from you or was something like that said by Intel or new reports?

How would someone be able to speculate that accurately by a simple comment by Broadcom that 18A is terrible?

By Reuters or Bloomberg. It's a recent report. It's in the Intel Q3 thread.

adroc_thurston said:
But it's just dLDOs.

It's how they used it that was unique.

Kepler_L2 · Nov 1, 2024

Hulk said:
It is getting hard for me to take Intel process timelines seriously because they seem to miss their deadlines so regularly. ARL disappoints architecturally and isn't on Intel 20A. Might be time for an AMD/Intel pair trade.

It just seems like IPC-wise x86 is nearly topped out. Zen 5 didn't show big gains and Lion Cove showed gains and regression. It seems more likely that the E cores will approach current ST iso frequency performance and peter out as well at that performance level as well, they just end up at that performance level in a more area efficient manner.

Without software help like new instructions or something I don't see how we get another 15 to 20% increase on a generation from either Zen 5 or LNC? 8 wide is already too wide, right?

On that same note, considering performance regression is LNC still +9% over Raptor Cove?

Zen5 is still much smaller vs Apple cores.

4-wide decode vs 10-wide
8-wide rename vs 10-wide
6 ALU vs 8 ALU
448 ROB vs 960

Hitman928 · Nov 1, 2024

Hulk said:
Okay. What is the IPC gain overall for LNC and Zen 5?

From the SPECint numbers we have, around 10% for Zen 5 and low single digits for LNC.

511 · Nov 1, 2024

Kepler_L2 said:
Zen5 is still much smaller vs Apple cores.

4-wide decode vs 10-wide

2*4 Decode 🙂

511 · Nov 1, 2024

Maybe Nova is still in planning phase if they need to launch by H2 2026 they can tape out A0 within 12 -18 months so Q1-Q2 25

DavidC1 · Nov 1, 2024

Hulk said:
It just seems like IPC-wise x86 is nearly topped out. Zen 5 didn't show big gains and Lion Cove showed gains and regression. It seems more likely that the E cores will approach current ST iso frequency performance and peter out as well at that performance level as well, they just end up at that performance level in a more area efficient manner.

Or, there's a lot to go and they haven't found a way yet. Don't think it's just conjecture people are saying BOTH of the x86 vendors suck in execution.

511 said:
2*4 Decode 🙂

Only when SMT is active.

That in itself is not significant though. Maybe 5% at best for average.

Kepler_L2 · Nov 1, 2024

511 said:
2*4 Decode 🙂

For 1T is just 4-wide.

511 · Nov 1, 2024

DavidC1 said:
Or, there's a lot to go and they haven't found a way yet. Don't think it's just conjecture people are saying BOTH of the x86 vendors suck in execution.

Only when SMT is active.

That in itself is not significant though. Maybe 5% at best for average.

These results says something else

https://twitter.com/x/status/1845436706025021930

511 · Nov 1, 2024

Also found these while searching

cannedlake240 · Nov 1, 2024

511 said:
You know his tweets are protected lol but those are major changes
Instructions decode 20B-> 24B increase in per cycle bandwidth
Two Taken Conditional branch
L2 cache improvement
It will be a Gracemont -> Crestmont Jump 3-7% IPC considering the small core is RPC IPC so higher IPC than a 5th gen Xeon core outside of AVX-512 🤣 and consuming way less power i hope Clearwater Forest is actually good with these

That seems like too many changes for what's essentially a node shrink tick core. Also wonder if the NVL e core naming change has actual meaning... It could signal a major Zen 5 like redesign for the uarch, which then can be iterated on to take the place of the current P core

igor_kavinski · Nov 1, 2024

Non-English YT video showing the 245K as more efficient and faster than 9600X:

But slower in games obviously.

No idea how accurate or true the bit about lower power consumption is, though.

Maybe Intel has a chance now to convince budget users to go for Arrow Lake?

EDIT: Scratch that! From same video:

Left ARL and right Zen 5 in PUBG. ARL is legendarily bad!

Guy trying his best to teach his followers that Zen 5 delivers more frames using more power

DAPUNISHER · Nov 1, 2024

20 review geomean

Hitman928 · Nov 1, 2024

igor_kavinski said:
No idea how accurate or true the bit about lower power consumption is, though.

Seems to not be true:

511 · Nov 1, 2024

DAPUNISHER said:
20 review geomean

View attachment 110776

While not mentioning power at all and Price
> 285k Nothing good about it
> 265K okay price and App performance if someone is buying Intel and does not care much about gaming it is the CPU to buy
> 245K would be fine if it was like 280$

igor_kavinski · Nov 1, 2024

511 said:
> 285k Nothing good about it

Maybe they can release a 280K SKU with 6P+16E to dial down the power consumption a bit or higher all core clocks for both P and E cores (maybe 290K in that case?).

GTracing · Nov 1, 2024

511 said:
These results says something else

Zen5 can execute 8 instructions per cycle. It can't decode more than 4 per cycle on a single thread.

Here's where chips and cheese discusses it in their Strix Point article.

Zen 5 can sustain higher instruction throughput than Intel Meteor Lake’s Redwood Cove P-Cores, but only for small instruction footprints or when both SMT threads are loaded. If only a single SMT thread is active, Intel’s larger 64 KB instruction cache and conventional 6-wide decoder can hand it a lead when code spills out of the micro-op cache.

Plenty of other cores can execute more instructions than they can decode, Zen4 for example.

AMD’s Strix Point: Zen 5 Hits Mobile

AMD’s Zen line has gone a long way since it brought AMD’s CPU efforts back from the dead.

chipsandcheese.com

SiliconFly · Nov 1, 2024

cannedlake240 said:
That seems like too many changes for what's essentially a node shrink tick core. Also wonder if the NVL e core naming change has actual meaning... It could signal a major Zen 5 like redesign for the uarch, which then can be iterated on to take the place of the current P core

Even if Darkmont has a mid single digit IPC increase and a slight bump in clocks, it should have ~80% the performance of a Lion Cove P core. Arctic Wolf should have higher IPC than a Lion Cove P core (but lower clocks). But even with lower clocks, it should have performance comparable to a Lion Cove P core.

MS_AT · Nov 1, 2024

Zen5 can sustain 8 ops from uop cache, but they have to be a mix of int / simd / mem. Games are more problematic bc for them uop cache is less effective. [up to 80 % hit rate for zen4 when zen 5 enjoys over 90% hit rate across spec int according to C&C]. That is to say 4wide decode doesn't seem to be immediate issue for Zen5.

dttprofessor · Nov 1, 2024

6P+16E/4P+16E non k should be a good choice.

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