If the TSVs didn't reach through the die, how do they connect the cache chiplets on zen 3 and zen 4? Doesn't it literally stand for "Through Silicon"?
Also heres the photographer himself and one of the die shots, suggesting they're structures related to the cache, he could be wrong though that was kinda my point with my first post lol. ¯\_(ツ)_/¯
A die can kind of be split into 3 general vertical sections. From top to bottom, you have the metal layers, the contacts (basically vias to the transistor area) and transistors, and the silicon underneath it all that traditionally had nothing in it. A TSV adds a via, or metal pathway in a vertical direction, through that underneath silicon to connect out the bottom of the chip, hence the name, through silicon via (TSV). Most TSVs in modern packaging go through the "empty" silicon and connect up to a very deep metal located near the transistors and not all the way to the top of the chip. So you are connecting from a close to transistor metal, to something on the backside of the chip and there are many metal layers above where the TSV stops.
For Zen 3 and Zen 4, the CCD is flipped upside down (flip-chip, which is typical for CPUs) so now the top of the chip is facing down and connects to the package from the top of the chip. The TSVs, which come out of the bottom of the chip, are now at the top and connect to the cache chiplet which is also flipped upside down, so you are stacking them "back to face," meaning the bottom of the CCD is interfacing with the top of the cache chiplet. Before it was known that the CCD is now on top, Fritzchens took those images and found what look very much like TSV structures in relatively the same locations and structure as Zen 3/4 (not exactly the same, but generally) and so most assumed that generally the cache/CCD stack was the same as previous generations.
Now that we know that the CCD is on top, this doesn't really make much sense. So, there are a couple of possible explanations that I see but they both bring up additional questions.
- The CCD isn't flipped upside down and connects through TSVs to the cache chiplet on bottom.
- This means that all the the signal and power/gnd connections have to come through the TSVs on the CCD but there doesn't appear to be enough of them in the right locations on the CCD for this to work. Additionally, the CCDs need to be able to get all of this from the top of the chip when there is no cache chiplet involved and the CCD is flipped upside down to connect to the package.
- When the CCD isn't flip chip, it causes it's own thermal issues that need to be worked around.
- The CCD is flipped upside down and gets all of the power and ground connections through the top of the chip, the same as when there is no cache chiplet.
- This means that all of the CCD power and ground signals have to be routed through the cache chiplet's TSVs.
- If this is true, what are those structures on the CCD that look very much like TSVs? If they are TSVs, what are they doing there? If they are not, what are they?
- One benefit is that they would provide some increased thermal conduction, but without them being near the hot spots of the chip, that doesn't seem like it would actually provide much benefit.
- How is the additional routing for the V-cache handled now that it has to be routed from the top of the chip down to the rest of the cache?
My best guess is that both chiplets are still flip chip and what appear to be TSVs on the CCD are actually TSVs that are an artifact of a previous plan to either keep the CCD on bottom, or put a third chiplet on top. This seems like a waste of die area to keep them in there if they weren't going to be used in production, but it's possible that it was determined that removing them wasn't worth the time and money to do so, versus the small amount of extra die area they take.
I hope this clears up any confusion as to what I've been posting.
Edit: Here's an example image from
Semi-analysis of what the TSVs would look like (generalized) for Ryzen products. The green/pink area are the metal layers, the grey/white/blue/brown is the contacts/transistor area, and the off-white or very light tan area is the "blank" silicon.