Typically, 4pm to 5pm Eastern time for posting the earnings release on the web site, and then, conference call about half an hour later.
2 PM PST ??
Yea, that article was long on opinion, assumptions and innuendo, but pretty short on hard facts. It certainly seems unlikely Intel would get such a large discount, and even less likely that TSMC would rescind it because somebody made a comment that offended them. If the discount was "real" wouldnt there have been some sort of contract signed that could not be voided?
Hitman, my problems with accepting your story:
For the first many years of Pat's reign, all of the biggest Intel news was about Intel building up and out its fab facilities. This included new EUV machines (first in the world!), new facilities, expansions on facilities.
Combine that with serious Intel/USGOV uptake and deal signing on CHIPS Act that committed them to being even BIGGER in the fab business for decades to come.
To me, they haven't behaved like a company that was ever, at any point in their outward actions, trying to divest and minimize their fab business.
Fair, I did not do a good job thinking this through. We are in alignment.
I wasn't paying attention to Intel during the Swan era. I've been wondering what outward actions suggest that Intel was trying to scale back on their fabs. I would be interested in what others can point to. The only thing I can think of it, the timing does appear to coincide with Intel losing "process leadership" (as they say). So we could say that they lost it because they didn't want it and stopped trying to hold it.
Also supported by leaked roadmaps. It seems they are doing it anyway with the 20A/18A fumble but Arrowlake-H with GT3 320EU graphics was planned for 2023 on N3.
Pat spends like a newly wed wife with her husband's credit card
That's what happens when an engineer runs a company! Personally I like working at companies spending like that but it makes less sense in Intel's position.Pat spends like a newly wed wife with her husband's credit card
I think a piece of this during Swans leadership was the failure of Intel’s first EUV process to meet the timeline for Aurora. This cost Intel about $300 million. Even earlier the failure of 10 nm caused the failure of the Optane business which was billions of dollars. Swan and maybe with the help of Keller identified the proprietary internal EDA tools as being a major problem. The internal EDA tools meant external customer couldn’t easily use Intel fabs, failure of Foundry 1.0 and Intel couldn’t move Ponte Vecchio to TSMC to meet timelines.From what I've heard, Swan and maybe even Krzanich had been building a relationship with TSMC as they saw Intel needing to transition to an outside foundry in the future. Under Swan specifically, they had started real negotiations and business dealings, with Swan seeming to favor an eventual move, in full or at least large part, to TSMC. This is where the first deal for Intel to do large volumes at TSMC began. It wouldn't surprise me at all if TSMC was offering Intel a large discount (probably not 40% but significant) to get their business, with Swan expressing a real interest in using TSMC long term. However, the board didn't like this and wanted to see someone who would work and invest in bringing Intel's fabs back to being a world leading foundry. This is a big part of why he got fired.
So, Pat comes in and tells the board that he sees a path for Intel to become the best foundry in the world, not just for Intel, but one that customers will flock to. The board likes this and hires him as CEO. Pat starts trumpeting his plan and talking about retaking foundry leadership and down playing TSMC's position as the now world leader in foundry tech. TSMC doesn't like this, not only because they find it insulting to their hard work and leadership position, but also because they don't want to just act as a crutch for Intel while Intel figures out its foundry issues and then become a competitor. With Swan, the vision was a slow transition to TSMC being the main foundry (or at least a substantial 2nd source) for Intel, but then Pat came in and killed that vision and started publicly dancing on its grave. That obviously soured the relationship with TSMC and whatever deal they had worked out to that point. Eventually, Pat had to make an "emergency" visit to Taiwan to try and smooth things over.
That's kind of what I've gathered from different whispers I've read and heard. Nothing is direct knowledge and some is filtered through some disgruntled ex-employees, so believe as much of it as you want. For myself, I don't believe the Reuter's article is fully accurate, but it's probably not that far off base either.
Come on, you know what my question was. You are just splitting hairs to be difficult. TSMC obviously has a huge capacity, the question still stands though if they could (or would be willing to) allocate enough wafers to AMD to supply 50 percent or more of the CPU market, especially now with Intel buying up a lot of wafers.AMD has no capacity.
The question should be, "how much capacity does TSMC have ?". Seeing that Intel is also using TSMC for their latest, then one could answer, "a lot", as AMD gaining will be Intel losing, so a sort of exchange.
If Intel loses marketshare and AMD gains same, the wafers will just shift between customers. Simple?Come on, you know what my question was. You are just splitting hairs to be difficult. TSMC obviously has a huge capacity, the question still stands though if they could (or would be willing to) allocate enough wafers to AMD to supply 50 percent or more of the CPU market, especially now with Intel buying up a lot of wafers.
That's what happens when an engineer runs a company! Personally I like working at companies spending like that but it makes less sense in Intel's position.
nope. it's the culture.Intel's downfall was largely caused by penny-pinching in R&D spending, and wasting the money on stupid acquisitions
Their downfall is they have no vision when they had technological leadership and cancelled any product that they deem to be bad for their existing margins.I'd argue it made sense. Intel's downfall was largely caused by penny-pinching in R&D spending, and wasting the money on stupid acquisitions. To get back from there, they had to spend a lot of money.
It would have made more sense if they had started all that spending instead of carrying out stock buybacks years ago.That's what happens when an engineer runs a company! Personally I like working at companies spending like that but it makes less sense in Intel's position.
This and,They couldn't secure Apple as a customer for Iphone.
This is connected. It took Intel until 2012(Medfield) to get a low power Smartphone out. They claimed Moorestown could do so but actually they mislead, because early reports were it could only get 4-5 hours of battery life, a significant gap compared to other phones. If they got Medfield out in 2010 instead of Moorestown, then application compatibility issue would have been lot less.Then they hamstrung their atom CPUs massively as to not compete with their core CPUs as to completely lose everything mobile. Intel had a massive lead in process and couldn't make a compelling mobile CPU the whole time the smartphone market was exploding.
This is it. Their culture has been messed up since the late 90's. Actually I would argue they had nothing after the founders have left. Craig Barrett also contributed to the decline.nope. it's the culture.
AMD has a contract for wafers with TSMC and the base wafer supply is a long term contract. These contracts are signed well in advance of actually production or knowledge of relative performance. My guess is that AMD is conservative with their base wafer demand because of the issues they had with GF in fulfilling their commitments and the penalties they paid.Come on, you know what my question was. You are just splitting hairs to be difficult. TSMC obviously has a huge capacity, the question still stands though if they could (or would be willing to) allocate enough wafers to AMD to supply 50 percent or more of the CPU market, especially now with Intel buying up a lot of wafers.
Intel can no longer self-fund their fab equipment as the price of moving to a new node has continued to go up exponentially. The lack of customer friendly EDA tools, and the lack of processes for on-boarding new customer designs will cost a good deal of time and money IMO. This is an under-lying architectural business issue inside of Intel that will delay their return to previous margins.I think a piece of this during Swans leadership was the failure of Intel’s first EUV process to meet the timeline for Aurora. This cost Intel about $300 million. Even earlier the failure of 10 nm caused the failure of the Optane business which was billions of dollars. Swan and maybe with the help of Keller identified the proprietary internal EDA tools as being a major problem. The internal EDA tools meant external customer couldn’t easily use Intel fabs, failure of Foundry 1.0 and Intel couldn’t move Ponte Vecchio to TSMC to meet timelines.
I believe that Swan traded Intel EUV tools for a contract to manufacture Ponte Vecchio and additional Intel products. ASML reported that some tools had been redirected when a ‘customers’ process was delayed. We know that Intel’s EUV process was delayed. There was a rumor that TSMC converted an R&D fab shell for the Intel tools. TSMC would want a contract for more than a year to take on the cost of those tools. My guess is there is a minimum of a three year contract. Pat may be looking to break some of that contract and pay a penalty to bring back wafers to in house.
A lot of speculation on my part.
... and Yet AMD managed >50% margins exclusively using TSMC nodes. Clearly Intel has some major structural issues that still need resolving. It isn't just about the chip designs IMO.I am looking at It and It doesn't look good, 15% gross margin?
As I said Intel will suffer because of moving production to TSMC.
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$9B loss before taxes and this is only for 3 months! That's 1132x more than a year before.
Foundry lost $4.4B more than a year before.
Truly not good at all from my limited understanding.
Cost of sales increased by $3.1B while revenue dropped by $0.9B compared to last year, when they still managed 42.5% margins.... and Yet AMD managed >50% margins exclusively using TSMC nodes. Clearly Intel has some major structural issues that still need resolving. It isn't just about the chip designs IMO.
It's pointless to go for market share, when you can easily lose It, If your next gen is a flop.
If you could go back in a time machine 10 years and tell Intel that, they would really appreciate it. Instead it has been a very expensive, very slow lesson to learn.Intel can no longer self-fund their fab equipment as the price of moving to a new node has continued to go up exponentially. The lack of customer friendly EDA tools, and the lack of processes for on-boarding new customer designs will cost a good deal of time and money IMO. This is an under-lying architectural business issue inside of Intel that will delay their return to previous margins.
I'm sure they knew, at the latest by TSMC's 7nm success in 2018. I've been thinking of a conspiracy theory that It would've been much more difficult to lie/manipulate/hide their fab issues from shareholders if they had to let other companies use the foundries (especially as once contracts were cancelled due to delays, the stock would've probably crashed). As long as AMD were behind, especially when they were using Global Foundries and TSMC was still behind, everything went well.If you could go back in a time machine 10 years and tell Intel that, they would really appreciate it. Instead it has been a very expensive, very slow lesson to learn.