Discussion Intel Nova Lake in 2026: Discussion Threads

Tigerick · Nov 3, 2024

With Pat pretty much confirm the existence of Nova Lake; let's started new thread about Nova Lake, the successor of Arrow Lake.

Even though Nova Lake is still two years away (currently target for Q4 2026 release), my source has provided more information below:

Once again, Intel will change the tile methodology of Nova Lake. The IMC no longer inside CPU tile, it is going to be integrated inside SoC tile. Nova Lake's SoC tile also going to integrate GPU as well. Since GPU is not considered priority for desktop and high-performance laptop chip, it makes sense for Intel to integrate GPU into SoC tile. That's mean Intel is able to reduce the total amount of tiles from four to three. Yep, considered this as ARL v2.0.
Higher NGU (new term for NoC of SoC tile) and ring clocks should fix the memory latency issues, we shall see.
The top-end SKU of NVL-S / NVL-HX will integrate V-cache similar to AMD's X3D. My source can't confirm the amount of L3 cache but the recent leaks about 144MB seems valid. This is going to be fourth tile on top (or bottom?) of current three-tile SoC.
Currently, NVL platform will support up to 128-bit DDR5-7200, the same memory speed AMD would support for upcoming Zen6.
Both Intel's NVL and AMD's Zen6 are targeting for Q4-2026 release.
As for process node, well Intel will definitely try to use IFS but as Pat said there are going to have some tiles that are made by TSMC, we should hear more in the future.

Unknown: Core count
My source known about core count of NVL and Zen6, but he won't reveal to me yet. He did mention both NVL and Zen6 are having much higher core count than current one. He also mentioned NVL going to have more core count than canceled 8+32 of ARL.

Bonus: AMD's Zen6
Beside higher core count, Zen6 is still targeting for Q4-2026's release; same timings as NVL.

Zen6's CCD will be fabbed by N3 family, most likely N3P.

That's all I know atm, enough to start the discussion about upcoming Intel's Nova Lake.

MS_AT · Nov 3, 2024

While I understand Zen6 will be limited to 128b DDR interface due to promised AM5 support, it makes no sense for Intel to significantly increase the core count and stick to 128b DDR inteface. Especially since nobody expects mobo backwards compatbility from them.

CakeMonster · Nov 4, 2024

Tigerick said:
Both Intel's NVL and AMD's Zen6 are targeting for Q4-2026 release.

AMD's schedule has not been a regular as Intel's, I assume this is speculation about AMD.

GTracing · Nov 4, 2024

I wonder if Nova Lake will still use the ring bus or if they're updating it or maybe even ditching it entirely. The ring bus seems like it's one of Intel's weakest points. It's already bad with 12 stops and it's only going to get worse if they increase the core count.

AFAIK Intel is the only company that has anything like a ring bus. The way it works is each p-core (or 4 e-cores) gets a stop on the bus with an equal share of the L3 cache. When a core needs data in another core's L3, the data has to "hop" from stop to stop. Anandtech's Raptor Lake core-to-core latency charts show that the latency can vary depending on how many hops it has to take. In comparison, Zen4's core-to-core latency within a CCX is basically the same no matter which cores it's going between (with the exception of SMT threads). Core-to-core latency isn't super important for performance, but this shows how the cache hierarchy of the ring bus has some fundamental downsides with large core counts.

The AIDA latency of the 285k, 14900k, 14600k, and 9700x shows how bad the latency on Intel is. For memory latency, Zen5 matches Raptor Lake's memory latency even though Ryzen uses chiplets.

In my opinion the sooner they switch away from it the better.

dullard · Nov 4, 2024

The Nova Lake and Diamond Rapids CPUID were recently released: 13_00H, 13_01H. Not that it is important information, but maybe it'll help identify leaks later.
See table 1-1: file:///C:/Users/swhitney/Downloads/architecture-instruction-set-extensions-programming-reference.pdf

"Updated Table 1-1, “CPUID Signature Values of DisplayFamily_DisplayModel,” to add values for future processors supporting Nova Lake performance hybrid architecture and future processors based on Diamond Rapids microarchitecture."

lopri · Nov 4, 2024

What other topology is possible than rings? I thought AMD also used a ring-like traffic when it moved onto 8-core CCX.

Saylick · Nov 4, 2024

lopri said:
What other topology is possible than rings? I thought AMD also used a ring-like traffic when it moved onto 8-core CCX.

There's a lot more. Mesh. Hub. And then you have a bunch of interesting topologies like ButterDonut.

Thunder 57 · Nov 4, 2024

I always figured they would move to a mesh eventually as they already developed one for the higher core count CPU's.

trivik12 · Nov 4, 2024

Bionic did post this.

https://twitter.com/x/status/1850014338473680952

and that Coyote Cove is client version of Panther Cove X in Diamond Rapids.

GTracing · Nov 5, 2024

After digging deeper, I found that Zen3 does use a ring bus of sorts. So I was wrong about that. I still stand by my main point that Intel's ring bus is bad.

Now with eight cores per CCX, since launch, AMD has been extremely coy about telling anyone publicly how those cores are connected together. When asked at launch if the cores in a Zen 3 eight-core CCX were fully connected, AMD’s general attitude was ‘Not quite, but close enough’. This would mean something between a ring and something between an all-to-all design, but more verging on the latter.

...

In our testing, our results show that while AMD’s core complex is not an all-to-all connection, it also doesn’t match what we would expect from ring latencies. Simply put, it’s got to be more than a ring. AMD has been very coy on the exact details of their CCX interconnect – by providing a slide saying it’s a ring reinforces the fact that it’s not an all-to-all interconnect, but we’re pretty sure it’s some form of a bisected ring, a detail that AMD has decided to leave out of the presentation.

Does an AMD Chiplet Have a Core Count Limit?

www.anandtech.com

Discussion Intel Nova Lake in 2026: Discussion Threads

Tigerick

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MS_AT

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CakeMonster

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GTracing

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dullard

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lopri

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Saylick

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Thunder 57

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trivik12

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GTracing

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Does an AMD Chiplet Have a Core Count Limit?

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