Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

dttprofessor · Nov 7, 2024

511 said:
I

Test productivity 😅
No matter how bad 14900K was it was not a regression like ARL was ARL would have been salvageable without the -ve gains it had

ULTRA 285 HX (desk type)
Pat gives up the top gaming peoformance .

511 · Nov 7, 2024

dttprofessor said:
ULTRA 285 HX (desk type)
Pat gives up the top gaming peoformance .

It was Swan Idea they axed Ocean Cove with 30% IPC in favour of RWC💡

dttprofessor · Nov 7, 2024

511 said:
It was Swan Idea they axed Ocean Cove with 30% IPC in favour of RWC💡

I think ocean was used by the p core team to fool pat and fight against the E core team. Pat was right to reject it. General technology was used on E core, and PPA&PPW took off.

511 · Nov 7, 2024

dttprofessor said:
I think ocean was used by the p core team to fool pat and fight against the E core team. Pat was right to reject it. General technology was used on E core, and PPA&PPW took off.

Yes Pat is a former CPU Architect and one of the better one of his time not easy to be fooled

dttprofessor · Nov 7, 2024

The original GNR was redwood on Intel4, which was rejected by pat and changed to redwood+ on intel3, using some front-end technologies of lion cove. This adjustment is very meaningful, otherwise GNR will be a disaster.

dttprofessor · Nov 7, 2024

The biggest reason why GNR did not adopt lion cove was that the p core team could not deliver the hyper-threading function on time, and pat could not wait any longer. This may also be an important reason why the p core team was broken up and placed under administration.

OneEng2 · Nov 7, 2024

511 said:
Anyways RIP Intel in Gaming it has been never been more over 🤣

... but certainly gaming isn't "game-set-and-match" type of a thing.

DC and Laptop are, and Intel are doing

naukkis said:
Intel Panther Cove will bring APX, which basically should give x86 similar performance possibilities than todays ARM. x86 is currently lacking about 50% IPC. If Intel doesn't target that with Panther Cove they are just losing their mind. And when they target that kind of high IPC they pretty much have no other option than drop SMT.

If they change their mind and re-introduce SMT they basically confirm that they have failed all their design targets and have gone to damage limitation mode.

In order to maximize ILP in a processor, you always need more execution units than a "normal" load will give in order to keep IPC high. This leaves execution units just sitting idle in many parallel load apps. This is where SMT fills in the gaps. SMT provides higher performance by running another thread through those unused execution units. It has been found that SMT provides up to 40% higher performance with only 5-10% die size penalty and very little increase in power.

I can't think of any reason why SMT would not be a good idea, especially in highly threaded workloads.

Kocicak said:
I have no idea, but I believe it is impossible that AMD ran exactly the same platform for three consecutive years without updating it.

Now is a bad time for jumping ships, the next year you will be able to choose between a fixed CPU for LGA 1851 or even better CPUs for AM5 than are available today.

AFAIK, AM5 has remained the same and any processor that fits into AM5 since the first, will work in the current AM5 and vise versa. It's very un-Intel like.

I think for AMD, AM5 is getting long in the tooth though and expect to see another socket for Zen 7. I think Zen 6 has already been confirmed for AM5.

Intel .... I wouldn't bet much on their socket stability. It has almost seemed like their strategy is to intentionally produce incompatibility between each new CPU release. It seems rare when they stick with a socket for more than 3 releases of a CPU

cannedlake240 · Nov 7, 2024

dttprofessor said:
The original GNR was redwood on Intel4, which was rejected by pat and changed to redwood+ on intel3, using some front-end technologies of lion cove. This adjustment is very meaningful, otherwise GNR will be a disaster.

RWC+ is a myth, Intel fellow and Xeon architect confirmed this in an interview with Cheese, that the only biggest differences are AMX and AVX512. Unless of course one deems those changes substantial enough to call it a RWC+

naukkis · Nov 7, 2024

OneEng2 said:
... but certainly gaming isn't "game-set-and-match" type of a thing.

DC and Laptop are, and Intel are doing

In order to maximize ILP in a processor, you always need more execution units than a "normal" load will give in order to keep IPC high. This leaves execution units just sitting idle in many parallel load apps. This is where SMT fills in the gaps. SMT provides higher performance by running another thread through those unused execution units. It has been found that SMT provides up to 40% higher performance with only 5-10% die size penalty and very little increase in power.

I can't think of any reason why SMT would not be a good idea, especially in highly threaded workloads.

Biggest reason is that SMT doesn't give you 40% more performance. It gives you 140% performance of two combined threads vs 100% single thread. So to use SMT you are giving up, in this example, 30% thread performance. And only reason for big cores to exists is to aim high thread performance. Without that need they can have much more performance from same silicon area by using more smaller cores. SMT is useless.

511 · Nov 7, 2024

cannedlake240 said:
RWC+ is a myth, Intel fellow and Xeon architect confirmed this in an interview with Cheese, that the only biggest differences are AMX and AVX512. Unless of course one deems those changes substantial enough to call it a RWC+

Well a move from Intel 4 -> 3 is enough to call it a plus

igor_kavinski · Nov 7, 2024

naukkis said:
Biggest reason is that SMT doesn't give you 40% more performance. It gives you 140% performance of two combined threads vs 100% single thread. So to use SMT you are giving up, in this example, 30% thread performance. And only reason for big cores to exists is to aim high thread performance. Without that need they can have much more performance from same silicon area by using more smaller cores. SMT is useless.

So IBM with their Dynamic SMT implementation and AMD killing Intel in y-cruncher nT workloads with just a 9800X3D's SMT vs. Intel's SMT-less cores is all happening somewhere in a galaxy far, far away

Simultaneous multithreading (SMT)

Markfw · Nov 7, 2024

igor_kavinski said:
So IBM with their Dynamic SMT implementation and AMD killing Intel in y-cruncher nT workloads with just a 9800X3D's SMT vs. Intel's SMT-less cores is all happening somewhere in a galaxy far, far away

Simultaneous multithreading (SMT)

View attachment 111196

Have it done with a 20 core AMD (or 16 WITH smt) and see what happens.

DavidC1 · Nov 7, 2024

igor_kavinski said:
So IBM with their Dynamic SMT implementation and AMD killing Intel in y-cruncher nT workloads with just a 9800X3D's SMT vs. Intel's SMT-less cores is all happening somewhere in a galaxy far, far away

IBM doesn't view SMT as "icing on top of a cake" as AMD/Intel does so they aren't directly comparable. Their SMT adds 20-30% transistors to the core to get lot more out of it. But their POWER lineup is used for Big Iron/Transactional computers so it benefits a lot.

dttprofessor said:
The original GNR was redwood on Intel4, which was rejected by pat and changed to redwood+ on intel3, using some front-end technologies of lion cove. This adjustment is very meaningful, otherwise GNR will be a disaster.

It doesn't look like that's the case, and it's just Redwood Cove with AMX and AVX-512. Some speculated 8-wide is just the output of the uop cache and there hasn't been anything contrary.

Pat's claims of ten plus percent might just refer to clocks.

OneEng2 · Nov 7, 2024

naukkis said:
Biggest reason is that SMT doesn't give you 40% more performance. It gives you 140% performance of two combined threads vs 100% single thread. So to use SMT you are giving up, in this example, 30% thread performance. And only reason for big cores to exists is to aim high thread performance. Without that need they can have much more performance from same silicon area by using more smaller cores. SMT is useless.

I call this "verbal diarrhea" or "Talking in circles".

Lets simplify the discussion a bit eh?

Neither SMT or more cores does ANYTHING for single threaded performance. If your use case is single threaded application performance ONLY, you don't need SMT and you only need a single core.

Now, lets leave fantasy land for a minute....

If you need MT performance, you can:
1) Add more cores
2) Make one core handle more than one thread

Now, lets talk about this a minute.

Adding SMT provides up to 40% (in AMD's implementation) and likely much more in IBM's implementation. It does this at the cost of only a tiny amount of power, and 15% more die size per core.

Doubling cores provides almost 100% MT over half the number of cores BUT it cost 100% more die size and 100% more power.

Another thing to consider in your above totally incorrect conclusion on SMT is that many (most) DC software licensing is done on a PER CORE basis, so doubling the amount of cores ALSO doubles your software licensing. FYI, for those of you that have never purchased this level of software, the software is WAY WAY more expensive than the computer you run it on.

If it is Intel's intent to create next gen DC processors by the "more cores" approach ..... wow..... good luck to them and God have mercy on their souls.

In DC, there are two very real limitations.
1) Socket power
2) Licensing cost per core (customer price pain limit)

SMT is VERY important in MT in DC products. AMD has decided that it is important to have a single CPU core design that works for an entire generation of products across all markets. Intel has decided to have 2 different core designs.

While you may be able to get away with lots of little cores in the desktop where per core licensing rarely exists, the same approach will find you totally bankrupt in the DC.

AMD provides Turin and Turin Dense exactly for this reason. While Turin Dense greatly outperforms Turin in overall performance in many applications (more cores with SMT, but each core being less performant than normal Turin), it doesn't work for enterprise applications that charge on a per core basis. In these applications, having maximum performance per core (including MT) is the most important thing since (as I already stated) the licensing cost is MUCH higher (and usually happens on a recurring basis) than the hardware costs.

So to steal a phrase from Star Wars "You are greatly mistaken about a great many things".

Abwx · Nov 7, 2024

naukkis said:
Biggest reason is that SMT doesn't give you 40% more performance. It gives you 140% performance of two combined threads vs 100% single thread. So to use SMT you are giving up, in this example, 30% thread performance. And only reason for big cores to exists is to aim high thread performance. Without that need they can have much more performance from same silicon area by using more smaller cores. SMT is useless.

Contrary to your sayings SMT is very usefull.

Say a core that has 40% SMT gain and a firm that sell cores usage for VMs.

If there s two users with each a virtual core then it would require that both have their app loading fully a single core to have 70% of the ST perf for each user, but it s unlikely that both will have their app peaking at the same exact time and for same durations, so in practice both will have the equivalent of 100% of the max ST perf while there s actualy only 140% available from the core.

alcoholbob · Nov 8, 2024

Markfw said:
Intel ? Stability ? you are in the wrong universe, see the Raptor lake instability threads

I think he said chipset stability. AMD still hasn’t fixed their USB instability problems in AM5 (probably will have to wait for AM6 when they update the USB chipset), and people are still complaining about TPM bugs.

DrMrLordX · Nov 8, 2024

cannedlake240 said:
It comes up time to time in reddit threads. It's a rumor though, maybe the reason Forest line is being cancelled is because SMT is coming back to Panther cove-X

mikk said:
Exist50 told it, means it is most likely correct.

Okay, kinda makes you wonder why, though? Certainly validation costs/delays aren't the reason?

cannedlake240 · Nov 8, 2024

DrMrLordX said:
Okay, kinda makes you wonder why, though? Certainly validation costs/delays aren't the reason?

This wouldn't be surprising, wasn't there a rumor about Pat pressuring product teams for shorter time to market? When he took over all Intel products were constantly being pushed back with Sapphire Rapids being the most infamous example. Who knows, maybe if it wasn't for this approach, Granite rapids, SRF, ARL, Lunar all wouldve been Q1-Q2 2025

naukkis · Nov 8, 2024

Abwx said:
Contrary to your sayings SMT is very usefull.

Say a core that has 40% SMT gain and a firm that sell cores usage for VMs.

If there s two users with each a virtual core then it would require that both have their app loading fully a single core to have 70% of the ST perf for each user, but it s unlikely that both will have their app peaking at the same exact time and for same durations, so in practice both will have the equivalent of 100% of the max ST perf while there s actualy only 140% available from the core.

For security reasons single core threads should not be split to different users. As cloud providers usually just disables SMT even AMD does also offer high-core count Epycs without SMT to them.

511 · Nov 8, 2024

cannedlake240 said:
This wouldn't be surprising, wasn't there a rumor about Pat pressuring product teams for shorter time to market? When he took over all Intel products were constantly being pushed back with Sapphire Rapids being the most infamous example. Who knows, maybe if it wasn't for this approach, Granite rapids, SRF, ARL, Lunar all wouldve been Q1-Q2 2025

Sapphire was something else it was during Kranzichs time to be delivered and it took till pat to deliver.
Also other things he did like
the design was not getting free tape out
Accurate simulations for metrics
Pressuring to shorter time to market
Design not getting hot lots and many more lol

poke01 · Nov 8, 2024

so what is Intels answer to this?
Nova lake?

Intel dropped SMT at the worst possible time too. M4 Max CPU power consumption is around 60 watts in R23.

And you know what not a SINGLE M4 CPU test regressed. Intel start making your ship straight because if others start achieving this kind of performance in the Windows laptop ecosystem then it will be too late.

cannedlake240 · Nov 8, 2024

poke01 said:
so what is Intels answer to this?
Nova lake?

Intel dropped SMT at the worst possible time too. M4 Max CPU power consumption is around 60 watts in R23.

And you know what not a SINGLE M4 CPU test regressed. Intel start making your ship straight because if others start achieving this kind of performance in the Windows laptop ecosystem then it will be too late.
View attachment 111251

This comes up from time lol, the fact is that they have no answer... Royal core was their premiere uarch program aiming high ST perf and that got canned 4-5 years into development just this summer. Their next chance from rumors is the Atom based uarch that's targeting beyond 2028 timeline

511 · Nov 8, 2024

poke01 said:
so what is Intels answer to this?
Nova lake?

Intel dropped SMT at the worst possible time too. M4 Max CPU power consumption is around 60 watts in R23.

And you know what not a SINGLE M4 CPU test regressed. Intel start making your ship straight because if others start achieving this kind of performance in the Windows laptop ecosystem then it will be too late.
View attachment 111251

It will be around 20% if you factor the OS but Nova Lake P core should be at least 20-25% ST Improvement considering they will fix their IMC/Mem controller along with APX and additional changes.Also they are doing a Tick and Tock so it is to be expected otherwise I don't know what would happen to x86
I also expect AMD to be around 15-20 better

OneEng2 · Nov 8, 2024

naukkis said:
For security reasons single core threads should not be split to different users. As cloud providers usually just disables SMT even AMD does also offer high-core count Epycs without SMT to them.

Do you have a link on this? I have never heard of anything like this before.
Thanks.

Still, no matter how you slice it, or find a corner case where SMT can't be used, the fact still remains that SMT is a very good architectural element for achieving high performance in MT rich applications. Intel made a mistake by removing it as it cripples their ability to compete in DC where the most growth and highest margins exist.

511 · Nov 8, 2024

OneEng2 said:
Do you have a link on this? I have never heard of anything like this before.
Thanks.

Still, no matter how you slice it, or find a corner case where SMT can't be used, the fact still remains that SMT is a very good architectural element for achieving high performance in MT rich applications. Intel made a mistake by removing it as it cripples their ability to compete in DC where the most growth and highest margins exist.

there may be some edge cases otherwise we would not have options to disable SMT on SKUs

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