Lion Cove's true L1 is what they call L0. It's basically marketing. L1i is only 64KB with 5 cycle latency. And it's "L1" has 9 cycle latency. It's L2 class latency of Nehalem days.Oryon has a 192 KB L1i, and Lion Cove has a 192 KB L1d, rivalling the size of the Apple. They both use 4 KB page sizes iirc, so I don't think your statement is true.
Not goddamn iso node comparison. Full stop. Don't.The difference between a 19-stage processor and 9 stage one is only 27%.
Then you go look at ARM servers doing high core counts...... oh look far worse cache implementations......Lion Cove's true L1 is what they call L0. It's basically marketing. L1i is only 64KB with 5 cycle latency. And it's "L1" has 9 cycle latency. It's L2 class latency of Nehalem days.
ARM's way of caches and clocks are far superior. Apple achieves better performance with lot lower power. The ARM chips aren't that far behind either. It is embarassing.
The scientists making these have long noted that power required for memory accesses is a big limiter in making it perform better. Having large L1 is a very good basic idea, which can't be done on 5.7GHz processors without insane latency.
The difference between a 19-stage processor and 9 stage one is only 27%. And x86 vendors have to pull out all the tricks to get there. Small, high latency cache levels, lowered uncore clocks, stability issues. It's not worth it. And that gap is going to shrink further. At what point you have to ask: Is it worth it?
That's a good point about TTM and target markets. AWS Graviton4, Nvidia Grace and Google Axion, all use the previous gen ARM Neoverse V2 cores. So it seems ARM IP takes a while to land in the market.Or lets not be idiots and actually evaluate things with consideration to their TAM/target markets, different vendors are making different trade offs.
Yes and they pay a very large price for it, CPU's are a pretty small component in TCO servers of a server and that's ignoring software costs. So if i channel my inner DavidC1 then ARM are just Dumb Dumb Dumb..... yeah ?That's a good point about TTM and target markets. Both AWS Graviton4 and Google Axion use the previous gen ARM Neoverse V2 cores. So it seems ARM IP takes a while to land in the market.
Speaking of ARM IP, ARM doesn't use very large L1 caches and shared L2 caches. Those are characteristics of Apple/Qualcomm's custom ARM CPU designs, which is what DavidC1 was talking about.
Eric Quinnell - XHot takes summary:
* ISA does matter (ie var length)
* OoO SMP beats SMT always
* > 2-3GHz is negative perf/watt
* no DMA in transport protocols
* grep/bash > python at text parsing
* OoO brp > OoO predicates, pick one
Quinnell spent nearly four years at Tesla, after stints at Arm, Samsung Austin R&D, and AMD. At AMD, he worked on the low-power x86 architecture that went into the PS4 and Xbox One. He currently works at Amazon AWS.
Fully agreed. There are some who argue that ISA doesn't matter, which is clearly wrong.ISA does matter (ie var length)
I believe SMP stands for Symmetric Multi Processing;OoO SMP beats SMT always
That explains why Apple hasn't implemented SMT, and why they have such large Re-Order Buffers.(2) I have come across various people who have posited that Apple's P cores do not have SMT since they have a very large ROB. I'll try post links to the OPs who said so -I can find them, but the idea is that the need for multithreading is eliminated since the core is very good at Out-of-Order execution. Is this correct?
What does brp stand for?OoO brp > OoO predicates, pick one
LOL. Ok, all this theory sounds great on paper, but obveously there is something wrong with it. Here is what happens when ARM 192 core meets Zen 5c 192 core: https://www.phoronix.com/review/amd-epyc-9965-ampereone#google_vignetteLion Cove's true L1 is what they call L0. It's basically marketing. L1i is only 64KB with 5 cycle latency. And it's "L1" has 9 cycle latency. It's L2 class latency of Nehalem days.
ARM's way of caches and clocks are far superior. Apple achieves better performance with lot lower power. The ARM chips aren't that far behind either. It is embarassing.
The scientists making these have long noted that power required for memory accesses is a big limiter in making it perform better. Having large L1 is a very good basic idea, which can't be done on 5.7GHz processors without insane latency.
The difference between a 19-stage processor and 9 stage one is only 27%. And x86 vendors have to pull out all the tricks to get there. Small, high latency cache levels, lowered uncore clocks, stability issues. It's not worth it. And that gap is going to shrink further. At what point you have to ask: Is it worth it?
There's no difference between VIPT and PIPT when the cache is small enough, and this is where the implementation becomes much nicer. Hence, the 48 KiB Zen 5 L1D$ and the 48 KiB Lion Cove "L0" D$, which use 4K page sizes, are both 12-way PIPT.
When the first-level cache uses VIVT, it requires some alias analysis hardware to handle duplicate instances of the same cache line, and this hardware does not come for free.
Well, the thing is that what matters is what people are usually brushing aside What mostly gets discussed is the decode [fixed vs variable instruction length] but things like memory ordering or architectural registers are brushed aside.ISA does matter.
I don't think they should be compared directly. The biggest promise of SMT is that when you have 8C8T CPU with little area cost you can make it 8C16T and get noticeable boost in PPA, not that SMT should be preferable to SMP.OoO SMP > SMT
We don't know if Apple will implement SMT in the future. It seems so far they did not feel a need to do so. But if gigantic ROB alone would be a key to higher performance then Intel should have stayed ahead of AMD, as every Intel P-core had bigger ROB than contemporary AMD equivalent if I am not mistaken.That explains why Apple hasn't implemented SMT
Having large L1 is a very good basic idea, which can't be done on 5.7GHz processors without insane latency.
And their huge L2 cache.IBM Z15 says hi, 128KB L1 with 4-cycle latency @5.2Ghz on 14nm node. It's doable, x86 vendors are just not at leading edge of designs.
you forgot to mention power and area numbers.IBM Z15 says hi, 128KB L1 with 4-cycle latency @5.2Ghz on 14nm node. It's doable, x86 vendors are just not at leading edge of designs.
you forgot to mention power and area numbers.
Actually as I recall Z15 goes even further beyond when it comes to power and area. It's even bigger and hotter than any x86 chip yet built. Only 12 cores in a massive 700mm² die.Power wise x86 cpus puts everything possible and more to drive those max boost clocks. And area is that problem with cache size versus latency - signal delays limits area available for cache. x86 small L1 caches aren't technologically limited but designs choices. And those design choices need to change as rivals are better.
Actually as I recall Z15 goes even further beyond when it comes to power and area. It's even bigger and hotter than any x86 chip yet built. Only 12 cores in a massive 700mm² die.
Intel doesn't deploy them all under 5 lb heatsinks with 20k rpm fans. And if IBM CPUs fail everyone using them has them under a maintenance plan, of course you'd never hear of it.Intel tuned Alderlake beyond silicon limitations. I haven't heard that IBM mainframes are dying same way.
Intel doesn't deploy them all under 5 lb heatsinks with 20k rpm fans. And if IBM CPUs fail everyone using them has them under a maintenance plan, of course you'd never hear of it.
You can more easily have a massive L1 of your plan is to have 12 cores instead of say 60 cores in a reticle limit.
14nm Z15 core without L2: 15.96mm²That IBM z-core isn't any bigger excluding L2 cache than x86 cores manufactured on same kind of process targeting same frequencies.
Oh hell no.Power wise x86 cpus puts everything possible and more to drive those max boost clocks
This is like arguing Core 2 was a bad server CPU versus Opteron. Then when they put a proper uncore with Nehalem, it left Opteron in the dust.Yes and they pay a very large price for it, CPU's are a pretty small component in TCO servers of a server and that's ignoring software costs. So if i channel my inner DavidC1 then ARM are just Dumb Dumb Dumb..... yeah ?
There's this too. Design and execution trumps ISA. Right now ARM vendors have both.IBM Z15 says hi, 128KB L1 with 4-cycle latency @5.2Ghz on 14nm node. It's doable, x86 vendors are just not at leading edge of designs.
LOL. Ok, all this theory sounds great on paper, but obveously there is something wrong with it. Here is what happens when ARM 192 core meets Zen 5c 192 core: https://www.phoronix.com/review/amd-epyc-9965-ampereone#google_vignette
ARM is beaten badly .... and nearly across the board in every benchmark .... and by significant margins.
I think too much time is spent on synthetic benchmarks, and theoretical performance that don't translate into real world performance.
I'm just saying, there's more to the picture than being painted here.
Not sure if "manufactured on same kind of process targeting same frequencies" covers cell height differences.14nm Z15 core without L2: 15.96mm²
14nm Skylake core with L2: 7.9mm²
It's not even close? I don't know what to say.
But thats the point , you cant do that with good performance because you have to have a cache control protocol that actually works across that. So then when you go and look at the latest ARM large scale fabrics they are significantly worse for data locality then what AMD are doing let alone what the ARM client cores look like.That's a terrible take. You're comparing a state of the art x86 core against a core far worse than the state of the art in ARM land. Put 192 M4 cores together with the same amount of inter-core communication and memory controller resources that the Zen 5c Epyc has and you'd see a totally different story. Or for a comparison where both sides are fighting with one hand tied behind their backs put 192 Bulldozer cores up against that AmpereOne.
Your example has absolutely nothing to do with "ARM not being able to translate between synthetic benchmarks and real world performance" and everything to do with AmpereOne having a crappy core, and its marketers having cherry picked a few benchmarks that show it off in the best light.
Yes I know what I'm suggesting to compare with doesn't exist, but it isn't because Apple couldn't build that 192 core monster it is because they have no interest in competing in the high end server market (or for that matter in the low end server market)
I'm not suggesting here that ARM is inherently superior, but the take some have that ARM's performance is only applicable to mobile and laptops and synthetic benchmarks, but it is unsuited for "real world performance" in high end gaming/workstation/servers is laughable.