Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

511 said:

Yes but during the start phase it was with N3 and no one at intel knew about the future of the nodes and they would turn to be better

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Even if they can, I don't think they should do it just cos they can. Cos, that amounts to back-porting. Reminds me of Rocket Lake. meh

Back-porting sounds good on paper. But not in reality imho.

SiliconFly said:

Back-porting sounds good on paper. But not in reality imho.

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Any other example of that from history? Rocket Lake could've been awful execution and bad luck combined.

igor_kavinski said:

Any other example of that from history? Rocket Lake could've been awful execution and bad luck combined.

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Zen5, Maxwell.

DavidC1 said:

Why? Bypassing DLVR means under load you don't have the losses due to going through the linear regulator.

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What type of pdn intel used in arrow lake?

SiliconFly said:

Even though it's portable (node agnostic), it still takes a significant amount of (engineering) effort, time & money to fab it in a new node. Time & money is something Intel doesn't have at the moment.


Modern cores are mostly portable across nodes. But sadly, portable doesn't mean easy and/or cheap in this context.

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It is crazy to expect you can just "change compilers" and create the same core on a completely different process. "Portable" is most certainly a relative term. In the case of modern processors, I would agree that using common design tools helps a processor to be more portable as long as we realize that "less work" means "less than ground up" and not "Cheap and Easy to do".

adroc_thurston said:

No.
Intel picked N3 because it was the best node available. That's it!

Nope, someone like ARM serves reference physical implementations yearly for a whole bunch of cores, for a pile of very different nodes.

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Intel didn't "PICK" N3 at all. They "picked" their own process ..... but it wasn't ready. Intel fell back to N3B. Additionally "best"? Best how? I believe that the only metric that N3B exceeds N3E in is transistor density, but it does this at a cost disadvantage. If you mean that N3B is "best" because it cost the most, then I would agree .

OneEng2 said:

Intel didn't "PICK" N3 at all

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Yeah they did.

OneEng2 said:

They "picked" their own process ..... but it wasn't ready

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No they didn't.

OneEng2 said:

Intel fell back to N3B

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No they didn't.

OneEng2 said:

Additionally "best"? Best how?

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Best xtor performance.

OneEng2 said:

I believe that the only metric that N3B exceeds N3E in is transistor density, but it does this at a cost disadvantage.

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N3e did not exist when the decision was made.

N3B is the only choice for intel in 2021-2022,N3E not for HPC.

dttprofessor said:

N3E not for HPC.

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It very much is.
What do you think Turin-D is for?

adroc_thurston said:

It very much is.
What do you think Turin-D is for?

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Turin D is N3E

Wouldn't porting Lion Cove/Skymont from N3 to Intel 3 be more of a "side" port since the nodes are similar feature-wise?

Yes but there will be cost associated with it and money is something they don't have rn

Hulk said:

Wouldn't porting Lion Cove/Skymont from N3 to Intel 3 be more of a "side" port since the nodes are similar feature-wise?

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They're not even remotely similar nodes. i3 is ~N5p on all metrics.

adroc_thurston said:

They're not even remotely similar nodes. i3 is ~N5p on all metrics.

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Nope lol the PPW is N3 levels but the Area is N4 levels

511 said:

Nope lol the PPW is N3 levels but the Area is N4 levels

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Who said that

adroc_thurston said:

Who said that

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Semiwiki
This one has link for techinsights if you have the subscription 🙂

Finally opened the link but on mobile 😅
Here is the link
Here are the images you can read the article
The density numbers are way off compared to actual number for TSMC in this
https://www.angstronomics.com/p/the-truth-of-tsmc-5nm take them with a grain of salt unless they are comparing 1-1 fin library for N3 node

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511 said:

https://www.angstronomics.com/p/the-truth-of-tsmc-5nm take them with a grain of salt unless they are comparing 1-1 fin library for N3 node
View attachment 111922

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Yea I'm pretty sure the i3 vs N3 comparison here is comparing intel HD cell (of unknown fin layout) vs a N3 1-1 fin cell. According to this site: https://fuse.wikichip.org/news/7375/tsmc-n3-and-challenges-ahead/, N3E 2-1 fin library only has a density of around 215 MTr/mm^2.
To my knowledge no TSMC n3 variant has a 2-1 fin cell which is more than 5-10% denser than N3E so the graph must be either making a mistake or using a 1-1 fin cell to represent TSMC N3 density which doesn't make sense unless there is a 1-1 fin HD cell that is already widely available and used from TSMC.

The comparison in the first place even using the correct 2-1 HD N3 density values is a bit misleading as it gives no mention of what the fin layout is like on the Intel 3 HD library, Is it 2-2 or something else? The intel 3 HD library has a height of 210nm compared to 240 of the HP library which is a proportionally small decrease meaning the fin layout is probably not radically different from the normal 3-3 found on the HP library so we're comparing a 3-2 or 2-2 intel 3 cell to a 1-1 TSMC cell which doesn't make sense to me. I mean I guess it doesn't matter anyways since TSMC having a working 2-1 or 1-1 HD library is itself part of the comparison between intel and TSMC 3nm densities but still it'd be nice to know since at least theoretically the transistor densities are limited by things like its different pitch sizes. Even if in reality it's up to which company can create the best library with their transistor technologies.

Also if you compare TSMC N3E HP library with a relaxed poly pitch of 54nm compared to intel 4/3 HP library, the theoretical densities are about equal so clearly the technologies are not as far apart as people think. I'm not entirely sure about all this stuff though since I'm pretty new to semiconductors, if anything I said was wrong please correct me.

ajsdkflsdjfio said:

Reply

Yea I'm pretty sure the i3 vs N3 comparison here is comparing intel HD cell (of unknown fin layout) vs a N3 1-1 fin cell. According to this site: https://fuse.wikichip.org/news/7375/tsmc-n3-and-challenges-ahead/, N3E 2-1 fin library only has a density of around 215 MTr/mm^2.

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There are only 2 fin libraries for Intel 3-3 and 2-2 for intel the comparison is with 2-2 libraries

ajsdkflsdjfio said:

Also if you compare TSMC N3E HP library with a relaxed poly pitch of 54nm compared to intel 4/3 HP library, the theoretical densities are about equal so clearly the technologies are not as far apart as people think. I'm not entirely sure about all this stuff though since I'm pretty new to semiconductors, if anything I said was wrong please correct me.

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You are mostly right regards to this

511 said:

Nope lol the PPW is N3 levels but the Area is N4 levels

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You don't have to compare theoreticals. Intel 4 Crestmont is 1.01mm2. N6 Crestmont is 1.46mm2. Intel 3 gets 10% density IF you use HD cells, and 0% if you use HP cells. So potentially a Intel 3 Crestmont is 0.92mm2

N6 is 18% density improvement over N7.
So,
N7 - 1.72mm2
N6 - 1.46mm2
N5 - 1.13mm2
Intel 4 - 1.01mm2
Intel 3 - 0.92mm2/1.01mm2

Intel 3 is anywhere from 11% to 22% in density improvement over N5. Intel 7 is slightly better than N7 in density. Gracemont is 1.59mm2.

adroc_thurston said:

They're not even remotely similar nodes. i3 is ~N5p on all metrics.

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You are likely wrong on the transistor performance part.

N5 is 15% over N7 and N3B is 10-15% over N5 and N3E is 15% over N5. So the question is how good is N7 over Intel 10nm?

Well, compared to the Intel 7 process, it's a little behind. From Intel 7 to Intel 3 we get 20% and 18%. I would say perf wise Intel 3 is a solid 10% or little more ahead of N3E.

Intel 18A would have been a solid lead over even N2, as it's talking about 10-15% over N3E, because the original specs had it as 20A being 15% over Intel 3 and 18A bringing an additional 10%. Now we lost that 10%, still it will still have the lead and probably match N2 with BSPD.

Density-wise 30% gain with 18A puts us roughly around N3.

dttprofessor said:

For CCG ,intel 3 is a expensive node.

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Why? Is that due to Intel needing as many wafers as they can get for Granite Rapids and Sierra Forest?

The funny thing is Zen5 would have been more perfomant on Intel nodes than on TSMC 🤣

511 said:

The funny thing is Zen5 would have been more perfomant on Intel nodes than on TSMC 🤣

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Yes, best performance for like 6 months and then their CPUs would've started degrading...

511 said:

The funny thing is Zen5 would have been more perfomant on Intel nodes than on TSMC 🤣

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I might be wrong, but this doesn't sound right at all.
We know part of it is Intel's P core being bad, but if you look at Granite Rapids vs Turin, GNR loses badly in all metrics and has a much lower base frequency. Not all of the difference is architectural imho. At "not 5GHz+" frequencies Intel 3 seems to be inferior to TSMC N4 in many metrics.

Kryohi said:

At "not 5GHz+" frequencies Intel 3 seems to be inferior to TSMC N4 in many metrics.

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Oh no! You really shouldn't have said that

DavidC1 said:

Density-wise 30% gain with 18A puts us roughly around N3.

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I'd say density wise intel 3 is already comparable to N3.

Redwood cove on intel 4: 5.33 mm^2 (5.33 on semianalysis 5.05 according to reddit post i used for lunar lake) Lion cove from lunar lake on N3B: 4.53

Assuming the blue blocks in both die shots are the raw data blocks for the l2$, by comparing pixel counts in the blocks versus total die shot you get .97 mm^2 for Redwood Cove (using 5.33 not 5.05) and 1.04 for Lion Cove.

Lion cove has 2.5 mb of l2 cache per core while redwood cove has 2mb. which is a 25 percent increase of 1.25x. Multiply the cache area for Redwood cove by 1.25x to get the theoretical area for 2.5mb l2 cache on intel 4: 1.215 mm^2.

Comparing the theoretical area of 2.5mb l2$ on intel 4 vs n3b = 1.215/1.04 = 1.17 = 17 percent more dense, this logic seems wrong but I double checked and that is one way to derive density difference of A over B, by dividing area of x transistors of B of x transistors over A. As a rule if A is 8% more dense than B, then B takes up 8% more area than A for x transistors.

I'm not sure if there is a significant difference between the designs of the L2$ data blocks of Redwood Cove and Lion Cove but in my opinion, the design of the raw data blocks of cache seems to follow established design patterns and thus would not have significant architectural changes that muddle up the waters.

Anyways the fact that N3B is only 17 percent denser than intel 4 is a pretty big deal, and I think different than the picture that most people have in their minds of intel vs tsmc process progress. In addition to this, N3B is a less widely used (and more expensive) variant of TSMC's N3 family, it is around 8% more dense than N3E, which I would say is the most common N3 node being produced. N3P seems to be pretty popular as well, and that offers only a 1.04x density over N3E meaning it is also around 4% less dense than N3B.

If you compare N3E vs Intel 4 in this theoretical scenario: N3E is only 8 percent more dense than Intel 4 when comparing 2.5 mb l2$
Comparing N3P vs Intel 4 uses the same method, I didn't calculate it but IDK something like 10% more dense than intel 4.

Now let's factor in that Intel 3 has HD libraries that are 10% more dense than Intel 4. Redoing the original calculations we find that N3B (denser than N3E and N3P) is only 6% denser than Intel 3 HD libraries. To be fair this comparison isn't exactly fair as it's assuming that 2.5mb l2$ on intel 3 would be purely using HD cells but still. If you calculate it against N3E and N3P you find that intel 3 HD is on par or denser than those N3 variants.

Now of course through publicly available TSMC and Intel density figures you would assume this difference would be much larger, but I believe that the on-paper difference between the density of Intel 4/3 nodes and TSMC N3E are largely due to TSMC offering an actually high density library using a 2-1 fin arrangement which is around 32% more dense than their HP high performance library, while Intel 3's "HD" library is only 10% denser than their HP library leading me to believe it isn't prioritizing density as much as TSMC's 2-1 fin=flex offering. Intel markets using their high density(not really) library densities, while TSMC markets their 2-1 fin or even 1-1 true high-density libraries as the face of N3 achieved densities. Either way in reality it is shown that at-least in client computing chip design, TSMC's N3 designs are not all that much denser than intel 4/3 designs especially if you are comparing N3E or N3P versus intel's nodes with only a 10% or less gap (at least in cache density) between intel 4 and N3E/N3P.