Would a new IOD improve SPEC2017 scores?AMD usually uses SpecINT2017 as the base for its IPC claims.
The are a few ways that a new I/O die could increase performance.Would a new IOD improve SPEC2017 scores?
Interesting but I don't think so. At least going by the latest IPC suggested in zen 5 where it seems like they explained the upcoming ipc based on what the core was capable of, but without the limitations of the IOD. Worked against them for zen 5 maybe work for them with zen 6?• New IOD
• Frequency Increase
I have a question: Doesn't the performance uplift brought by the new IOD fall into the category of "IPC" ?
The main counter point to a new IOD is AMD's history of the cheapest possible solutions. They have done "the XT" twice, why not with Zen 5 too?Also, while I think that modifying the IOD of Zen 5 might well unlock more performance for AMD with minimal effort, I wonder if the Zen 5 front end needs modified to really take advantage of additional bandwidth?
There is something planned for next year that isn't the cheapest possible solution. But no one will want it and I'm not convinced it'll help much.The main counter point to a new IOD is AMD's history of the cheapest possible solutions. They have done "the XT" twice, why not with Zen 5 too?
They could bring "wide GMI" from sIOD over to cIOD; doesn't seem costly. But this would only improve memory bandwidth, not memory latency, while the latter matters more to the client segment.The main counter point to a new IOD is AMD's history of the cheapest possible solutions.
As @GTracing already indicated the score already differs between different Zen 5 products. Epyc Turin famously achieves ~40% while X3D less client chips don't even manage 10% to the disappointment of pretty much everybody.Would a new IOD improve SPEC2017 scores?
But a very large portion of that difference is because client Zen 5 runs up against frequency walls while Turin isn't. How is it going to fix that?As @GTracing already indicated the score already differs between different Zen 5 products. Epyc Turin famously achieves ~40% while X3D less client chips don't even manage 10% to the disappointment of pretty much everybody.
The are a few ways that a new I/O die could increase performance.
I might be missing some, but they all basically come down to improved bandwidth and latency for the L3 cache or ram.
- Lower memory latency
- Higher ram bandwidth
- Higher bandwidth from the I/O die to the CCD
- Lower latency between CCDs
With that in mind, the question becomes does SPEC benefit from better L3 and RAM? If you look at chips and cheese's 9800X3D vs 9950X benchmarks, I would say yes.
AMD's 9800X3D: 2nd Generation V-Cache
Following the first generation of V-Cache found in the Zen 3 and Zen 4 X3D SKUs, AMD is now following up with the second generation of V-Cache which is a major change for AMD in terms of packaging.chipsandcheese.com
The cadence has slowed over time. I am not surprised, in fact I argue that it is a waste of time and energy to design something new without the advantage of a significantly improved process to do it on.AMD makes a new core every 2 years for the past 8 years, why are you surprised that Zen 6 is coming out 2 years after Zen 5?
Unless we are talking about pure single threaded performance ..... which I think is silly in this day and age, it is my opinion that performance per clock is a much better gauge of the design of a core. This is why I keep questioning the assertion that Skymont is a great idea for a unified design. Only when viewed from a single threaded POV is this true. Once you are talking about MT applications, how much performance per core does Skymont attain compared to Zen 5c with SMT?What exactly is termed IPC?
(1) Is it the basic core processing "X" instructions for "Y" cycles = X/Y IPC?
(2) Is it the wider CPU processing "X" instructions for "Y" cycles = X/Y IPC?
(3) Something else?
(2) = real world usage for user. IOD improvements apply here but not in case (1), which seems to assume zero external latency effects. I would assume feeding the cores as relevant to IPC, but it seems core designers think more narrowly (my impression) as in case (1).
I am not complaining about AMD's efforts to remain very profitable while Intel is burning through money like a drunken sailor (FYI, I have done this personally in a very literal sense ). Zen 5 manages to outperform everything Intel has to offer in nearly every way while doing it on a less expensive and less dense process node.The main counter point to a new IOD is AMD's history of the cheapest possible solutions. They have done "the XT" twice, why not with Zen 5 too?
No one here will want it perhaps. We are not the majority of customers. I see AMD gaining traction in the corporate laptop market next year by offering the absolute best performance per $. Intel has spent decades using its loss leader capability in one segment that they simply augment with a profit leader in another. They do this and squeeze AMD's market share and profit that has kept AMD from building up further and investing to become more competitive. I think that things have changed. Cheap is good sometimes.There is something planned for next year that isn't the cheapest possible solution. But no one will want it and I'm not convinced it'll help much.
The cadence has slowed over time. I am not surprised, in fact I argue that it is a waste of time and energy to design something new without the advantage of a significantly improved process to do it on.
The core die size did go up from 74mm2 to 80mm2 though. Additionally, Zen 2 was the first chiplet design and like Intel, AMD had latency issues in the first design that they fixed with Zen 3 giving basically the same design much better performance.Zen 2 to Zen 3 had great gains gen over gen and both were N7. That said I don't think AMD can gain much more with a better IOD die and fclk.
I don't know what you mean by "latency issues" but that's not what AMD says the IPC comes from.The core die size did go up from 74mm2 to 80mm2 though. Additionally, Zen 2 was the first chiplet design and like Intel, AMD had latency issues in the first design that they fixed with Zen 3 giving basically the same design much better performance.
Zen 5 is already at 5.7GHz. There's practically no room to grow there. They used up most of them in Zen 4. We aren't going to get another 10%. Intel literally kills Raptorlake to get there, and in Arrowlake a significant performance potential.Why do you think 10% performance is all that zen 6 will bring to the table? That's just the suggested IPC increase, there are other vectors for improved performance...
What's the size of Zen 4c without L2 cache? The performance per clock differences is 25-30% in Integer and 60% in FP. Gracemont clocks quite a bit higher though on the client part at 4.4GHz.This is why I keep questioning the assertion that Skymont is a great idea for a unified design. Only when viewed from a single threaded POV is this true. Once you are talking about MT applications, how much performance per core does Skymont attain compared to Zen 5c with SMT?
Cope?There's practically no room to grow there
Hell yeah juice the 3-2 finpile in.We aren't going to get another 10%
No?AMD had latency issues in the first design
I don't know what @OneEng2 had in mind particularly either. But when AMD highlights, for example, the changed cache prefetching policy of Zen 3, then this is about reduced latency. (See the middle part of page 5 of Ian Cutress' Ryzen 5000 deep dive.) Edit: I haven't looked up to which extent other items in that list, i.e. execution engine etc., were about reduced latency (versus improved throughput, although you hardly can look at either in isolation).I don't know what you mean by "latency issues" but that's not what AMD says the IPC comes from.
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On the other hand, they diversify their products and thus address more target markets or address markets better.The cadence has slowed over time. I am not surprised, in fact I argue that it is a waste of time and energy to design something new without the advantage of a significantly improved process to do it on.
AMD actually did say which 25 workloads they tested.What @moinmoin said. Also,
I don't know what @OneEng2 had in mind particularly either. But when AMD highlights, for example, the changed cache prefetching policy of Zen 3, then this is about reduced latency. (See the middle part of page 5 of Ian Cutress' Ryzen 5000 deep dive.)
BTW, AMD apparently didn't disclose what the 25 workloads for their 19% figure were. Hence it is impossible to say if these workloads were largely insensitive to the CCX change. Only then would the left side of this slide correspond well with the right side of the slide. (End note R5K-003: See e.g. press release at amd.com.)
Zen 5 is already at 5.7GHz. There's practically no room to grow there.
Yeah that 19% IPC uplift is BS because it's heavily gaming focused, that's not what you do when you want to assess average IPC uplift across many applications.AMD actually did say which 25 workloads they tested.
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I can see where better prefetching could be considering lowering latency, but that's clearly not what OneEng2 was talking about. Since he said the first generation chiplets were the issue and prefetching has nothing to do with chiplets.
Yeah that 19% IPC uplift is BS because it's heavily gaming focused, that's not what you do when you want to assess average IPC uplift across many applications.
Maybe it's truly 19% or so in Spec, but this test for sure was wrong if they wanted to show average IPC.
I think This is the immediate future. More non-homogeneous computing aimed at more specific work loads.On the other hand, they diversify their products and thus address more target markets or address markets better.
It basically matched for Zen 3. But if you haven't realized by now AMD does their marketing numbers backward. Engineers say what they achieved in spec and then the marketing bros pick a bunch of benchmarks and games to put on the slide such that the geomean is around the target given.Yeah that 19% IPC uplift is BS because it's heavily gaming focused, that's not what you do when you want to assess average IPC uplift across many applications.
Maybe it's truly 19% or so in Spec, but this test for sure was wrong if they wanted to show average IPC.
What kind of garbage post is this? 19% in games, 19% or so in SPEC, but it's all wrong if you look at "average IPC"?