Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

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Vattila

Senior member
Oct 22, 2004
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Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).



What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!
 
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Gideon

Golden Member
Nov 27, 2007
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Hmm, it seems AMD actually made its first 4-socket HPC server for MS with only CPUs and monstrous memory bandwidth available. 88x Zen 4 cores clocked at 4Ghz. Four of these have access to 450GB of HBM at ~7.0Tbps bandwidth. Nodes connected via InfiniBand.




I guess under the hood it's just a MI300 derivate with only CPU cores? (Sort of like MI300A but no GPU cores, binned to 88 cores, down from 96)
 
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LightningZ71

Golden Member
Mar 10, 2017
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It's possible that they are just choosing to disable them to increase yields. Hawk Point will broadly compete with Kraken on most metrics, but they need Kraken to have higher ASPs. The NPU will be the differentiator.

If they were really smart, they'd have done a Hawk Point part that, instead of having an NPU, had a 16MB LLC or just an infinity cache for the iGPU. That would have done well for them in handhelds in addition to the lower end of the laptop market.
 

jpiniero

Lifer
Oct 1, 2010
15,365
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It's possible that they are just choosing to disable them to increase yields. Hawk Point will broadly compete with Kraken on most metrics, but they need Kraken to have higher ASPs. The NPU will be the differentiator.

If they were really smart, they'd have done a Hawk Point part that, instead of having an NPU, had a 16MB LLC or just an infinity cache for the iGPU. That would have done well for them in handhelds in addition to the lower end of the laptop market.

The purpose of the NPU is so that OEMs can claim they are selling more "AI PCs".
 

Joe NYC

Platinum Member
Jun 26, 2021
2,672
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It's possible that they are just choosing to disable them to increase yields. Hawk Point will broadly compete with Kraken on most metrics, but they need Kraken to have higher ASPs. The NPU will be the differentiator.

If they were really smart, they'd have done a Hawk Point part that, instead of having an NPU, had a 16MB LLC or just an infinity cache for the iGPU. That would have done well for them in handhelds in addition to the lower end of the laptop market.

It would need a new die and new verification to add LLC, so more trouble than the benefit AMD will get out of these in terms of revenue.
 

LightningZ71

Golden Member
Mar 10, 2017
1,910
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I doubt that it even made it to a test fab. It probably existed in the modern day equivalent of a verilog simulator and got no farther. I don't doubt that there may exist a few test samples of Strix Point in it's original configuration however.
 
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