The latter. AFAIK RDNA 4 is not in any APU productWill Zen6 APUs (Medusa) have RDNA4 orRDN A5UDNA?
I wouldn't be surprised if it is RDNA 3.5Will Zen6 APUs (Medusa) have RDNA4 orRDN A5UDNA?
It's a mix AFAIK, but most are using a slightly upgraded RDNA3.5 uarch.Will Zen6 APUs (Medusa) have RDNA4 orRDN A5UDNA?
RDNA3.5 (or 3.75) in 2027? It's like Vega all over again.It's a mix AFAIK, but most are using a slightly upgraded RDNA3.5 uarch.
Were you hopin/plannin on running Alan Wake 2 with path tracing on a zen 6 APU 🤪RDNA3.5 (or 3.75) in 2027? It's like Vega all over again.
I really hope the Halo parts at least have UDNA. 40+CUs is definitely capable of RT (though probably nit path tracing)Were you hopin/plannin on running Alan Wake 2 with path tracing on a zen 6 APU 🤪
If the flagship is getting a 50% core count increase (16->24), then it's worth increasing the entry level part to 8 cores (33% increase, 6->8).12 core CCD's sounds reasonable for desktop and high performance laptop; however, I believe that half that (6 CCD) would be more than enough for many budget applications.
Seems like a 2 CCD 24 core 48 thread desktop Zen 6 would be quite a beast.
VVC is DOA like any other MPEG-LA codec since the dawn of AV1.With VVC we could have the same situation in 2027.
RDNA5 where it matters, 3.5 for luggables etc.Will Zen6 APUs (Medusa) have RDNA4 orRDN A5UDNA?
If it's real, it's probably something like 6C+6c ring layout.12 core CCD's sounds reasonable for desktop and high performance laptop
How ryzen r3 phenom for six cores ?If the flagship is getting a 50% core count increase (16->24), then it's worth increasing the entry level part to 8 cores (33% increase, 6->8).
Fair point in desktop and laptop.I'm not overly optimistic about more cores per CCD because of the skyrocketing node cost and the slow advancement lately (except for the c core parts).
We'll probably see some with 6 too, unless their yields are too good to make it worthwhile.Budget: 1x12 CCD with 8 or 10 active cores.
Bearing in mind that core count per CCD hasn't actually changed since Zen1 in consumer land.I'm not overly optimistic about more cores per CCD because of the skyrocketing node cost and the slow advancement lately
But does 12 cores make sense from a consumer perspective? And when you have Zen 6c cores available?A 50% boost is definitely within the realms of possibility at this point when we are on the verge of 2nm nanosheet nodes.
How does this work with AM5? Already we see Zen5 as having some main memory limitations.Bearing in mind that core count per CCD hasn't actually changed since Zen1 in consumer land.
aka since 14nm finfet.
A 50% boost is definitely within the realms of possibility at this point when we are on the verge of 2nm nanosheet nodes.
Strix Halo has been mentioned in the past on these forums as being a 'pipe cleaner' of tech that is being rolled out to Zen 6 consumer sku's. So there is a doubling of membw if the Strix Halo rumours are correct.How does this work with AM5? Already we see Zen5 as having some main memory limitations.
If we have a 50+ % increase in cores and another 10+ % throughput increase per core, where does that leave us? DDR5 10000+ needed?
As a comparison, SP5 has 12 channels serving 128 Zen5 cores vs AM5 having 2 channels with 16 cores maximum.
The bottleneck is not the memory speed or even IF speed but the link between CCD and IOD. Design wise CCDs are capable of two such links but in client chips only one is ever used.How does this work with AM5? Already we see Zen5 as having some main memory limitations.
Yes, Strix Halo will answer many questions.Strix Halo has been mentioned in the past on these forums as being a 'pipe cleaner' of tech that is being rolled out to Zen 6 consumer sku's. So there is a doubling of membw if the Strix Halo rumours are correct.
True, but the SP5 socket has max 10.67 cores/memory channel, also slower cores, still 50% more bandwidth/core than AM5 (max). Tells me, that at the limit, the cores with AM5 are starved. Strix Halo will show what's true.The bottleneck is not the memory speed or even IF speed but the link between CCD and IOD. Design wise CCDs are capable of two such links but in client chips only one is ever used.