Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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inquiss

Senior member
Oct 13, 2010
250
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No, I included that.
Ok, I don't think your logic is sound. I don't know why you'd buy a chip with the primary purpose of gaming and choose to prioritise the web performance over the gaming. You may be right with the configuration of course, but it won't be because of the logic in these replies.
 

DaaQ

Golden Member
Dec 8, 2018
1,568
1,139
136
What would stop someone from making a sort of "gaming frame" for iPhone that includes physical controls and on the backside some sort of cooling plate (whether thermoelectric or vapor diffusion w/ fans)

I suppose the hangup would be getting support from developers for what would be a low volume product, or products if more than one came out that worked differently. If Apple cared about hardcore gaming I suppose they could make the thing themselves and that would probably guarantee developer support.
The Motorola Droid Turbo Z??? The one with the Moto mods, already did that. Magnetic backside with contact points for a larger battery, JBL speaker, or a game pad controller with thumb sticks and buttons.
They ditched that for the Edge+ series.
 

gdansk

Diamond Member
Feb 8, 2011
3,276
5,186
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Ok, I don't think your logic is sound. I don't know why you'd buy a chip with the primary purpose of gaming and choose to prioritise the web performance over the gaming. You may be right with the configuration of course, but it won't be because of the logic in these replies.
It has gaming too. I don't understand the problem. Just make sure the game is on the right CCD when fine tuning the settings. And done. Best of both worlds until they solve the clock rate (they won't until they move all L3 off chip).
 

biostud

Lifer
Feb 27, 2003
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5,706
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I agree AMD is staying the course with one vcache ccd. However, having a faster non vcache ccd helping in web apps vs having gaming run smoothly, which is the selling point of the vcache models in the first place seems like a much better tradeoff than keeping the existing structure of a faster non vcache ccd.

Also, it may not be important in the end, but you're making an assumption that they're not saving the best binned CCDs for the higher end 16core vcache models. You're basing your assumption based on what can be done with single CCD models right now, you don't know what they can hit frequency wise with vcache yet.
In this phoronix test the 9800X3D is ~5% faster than the 9700X@105W and ~12% faster than the 9700X@65W (the mention an average of 9%), so the 3D vcache also helps in non-gaming tasks, which is why it could make sense to also release a dual vcache 9950X3D. They could for all sake and purposes release the two regular ones and the 9970X3D with dual vcache at a premium segment.

While not all workloads can benefit greatly from 3D V-Cache, there are many productivity/HPC/technical computing workloads that can. AMD is heavily promoting the Ryzen 7 9800X3D as a great gaming processor, which it is, but it's also much more than just a great gaming CPU. The continued strong showing of AMD 3D V-Cache across this mix of Linux workloads continues to build my excitement for further Ryzen 9000X3D CPU additions and then 2nd Gen 3D V-Cache on the AMD EPYC Turin side should be extremely interesting.

 

moinmoin

Diamond Member
Jun 1, 2017
5,145
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This is very counterproductive to squeezing the maximum amount of margin out of every available Si piece.
AMD should just do premium priced limited runs with much higher margins for the few people who would buy such at any price. Same with all kind of OC enabled Threadripper counterparts to Epyc chips. And sell them all only through their web store to cut out scalpers and avoid mixing those with the regular client products.

They won't ever do that anyway though.
 
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StefanR5R

Elite Member
Dec 10, 2016
6,056
9,106
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If the product is built so that the CCD with vcache is also the faster of the two CCDs, doesn't that make the scheduling much easier?
I'd say it makes it *easier*, but doesn't make it *easy*.
Today's operating systems just don't have information about memory access patterns of the various tasks to make this sort of decision all on their own.

Because the vcache ccd with the fastest cores will be allocated first?
First-come-first-served is not an appropriate approach in many cases. It may be a good-enough approach in several specific scenarios.

The CCD with v-cache is slower
It remains to be seen how the product will look like.
 
Jul 27, 2020
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Today's operating systems just don't have information about memory access patterns of the various tasks to make this sort of decision all on their own.
They don't bother, that's the actual problem. An OS has the best insight into how an application uses memory/storage and over several runs, it could cache most frequently accessed data long term and immediately load that up in RAM to get applications to run with max efficiency without waiting for the application to warm up. Users could opt to store caching profiles for their most important applications and all it would cost is storage space.
 
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StefanR5R

Elite Member
Dec 10, 2016
6,056
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(task scheduling on CPUs with inhomogeneous cache domains)
An OS has the best insight into how an application uses memory/storage and over several runs, it could cache most frequently accessed data long term and immediately load that up in RAM to get applications to run with max efficiency without waiting for the application to warm up. Users could opt to store caching profiles for their most important applications and all it would cost is storage space.
I disagree. Monitoring of these things — that is, main memory accesses of different concurrent workloads and how they interact with each other and with processor cache capacity and processor caching policy — takes nontrivial effort. And prediction of how the sum of running applications will behave is even harder, and would be highly speculative. (Remember what Niels Bohr said about Prediction.)

Edit:
(on a hypothetical CPU with 1 3DV$-CCD and 1 valilla CCD, with the former clocking at least as high as the latter)
one would no longer have to give hints which threads prefer cache and which threads prefer clock. But one would still have to give hints which threads are to be blessed to get to run on the good CCD and which threads shall take the back seat. Though in many cases such information already is provided, via scheduling priorities, and scheduling classes (interactive work versus batch jobs).
Re: scheduling classes — on the other hand, it *may* sometimes be more optimal to run a high-priority latency-sensitive interactive task on the low-cache CCD and a simultaneous low-priority non-interactive task on the high-cache CCD. That's if memory bandwidth demanding accesses of the latter task drag down memory access latency of the former task¹, but the access patterns are such that the interactive task is fine with 32 MB$ but the batch task happens to be greatly helped with 96 MB$.
________
¹) While these two concurrent workloads could have separate CCDs and thus separate processor caches, they would still be sharing the one memory controller.
 
Last edited:
Jul 27, 2020
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I disagree. Monitoring of these things — that is, main memory accesses of different concurrent workloads and how they interact with each other and with processor cache capacity and processor caching policy — takes nontrivial effort. And prediction of how the sum of running applications will behave is even harder, and would be highly speculative. (Remember what Niels Bohr said about Prediction.)
We will never know if no one tries. The monitoring of process related statistics might very well be a CPU intensive process in which case, the OS can allow the user to turn on "training" mode where the OS learns as much as it can about the user's typical usage over several days. Then once enough data has been collected, the training mode can be turned off and the CPU overhead of monitoring goes away.
 
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mzocyteae

Junior Member
Dec 29, 2020
10
12
51
AMD should just do premium priced limited runs with much higher margins for the few people who would buy such at any price. Same with all kind of OC enabled Threadripper counterparts to Epyc chips. And sell them all only through their web store to cut out scalpers and avoid mixing those with the regular client products.

They won't ever do that anyway though.
Retail threadrippers are sufficiently premium comparing to epyc (considering the volume discounts), yet the threadrippers are ridiculously handicapped.
 

pj-

Senior member
May 5, 2015
490
264
136
Probably reading too much into it but gamers nexus just uploaded their weekly news video and ended with a brief mention of the 9950x3d / 9900x3d release date rumor article from wcftech, conspicuously not mentioning the later leak about single vcache ccd, and he even specifically says they've heard that "AMD is planning a major rework of its implementation of dual ccd parts"


The preceding intel news item in the video was from yesterday, so I don't think its a matter of them filming before the newer rumor dropped, and doesn't seem like something he'd miss
 

Thunder 57

Diamond Member
Aug 19, 2007
3,079
4,873
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Probably reading too much into it but gamers nexus just uploaded their weekly news video and ended with a brief mention of the 9950x3d / 9900x3d release date rumor article from wcftech, conspicuously not mentioning the later leak about single vcache ccd, and he even specifically says they've heard that "AMD is planning a major rework of its implementation of dual ccd parts"


The preceding intel news item in the video was from yesterday, so I don't think its a matter of them filming before the newer rumor dropped, and doesn't seem like something he'd miss

I don't see AMD offering dual X3D versions. To me it just sounds like something someone pulled out of their bum and has been repeated so much it is being regarded as plausible. I don't think they could hit the right price with a dual X3D version. It would fix scheduling issues though.
 

biostud

Lifer
Feb 27, 2003
18,846
5,706
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I don't see AMD offering dual X3D versions. To me it just sounds like something someone pulled out of their bum and has been repeated so much it is being regarded as plausible. I don't think they could hit the right price with a dual X3D version. It would fix scheduling issues though.
If there is a market for 14900KS then I also think there is a market for a lineup for three pricing tiers 9900X3D, 9950X3D and 9970X3D (16c dual vcache)
 

biostud

Lifer
Feb 27, 2003
18,846
5,706
136
There still would be scheduling issues with threads migrating to the other CCD. Sure a vcache too but there would still be need to access the other CCD.
yes, but in a game like ACC, where the 7800X3D > 7950X3D > 7950X >= 7700X, then there is is no regression going from one CCD to two 7700X-> 7950X, but only having vcache on one CCD 7800X3D -> 7950X3D seems to only give you some of the difference between 7700X and 7800X3D, and especially the 1% lows are not improved as much.

So as long as the CCD's are similar, it might not matter to much with threads migrating.


 
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