Question Zen 6 Speculation Thread

maddie said:

How does this work with AM5? Already we see Zen5 as having some main memory limitations.

If we have a 50+ % increase in cores and another 10+ % throughput increase per core, where does that leave us? DDR5 10000+ needed?

As a comparison, SP5 has 12 channels serving 128 Zen5 cores vs AM5 having 2 channels with 16 cores maximum.

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maddie said:

Yes, Strix Halo will answer many questions.

True, but the SP5 socket has max 10.67 cores/memory channel, also slower cores, still 50% more bandwidth/core than AM5 (max). Tells me, that at the limit, the cores with AM5 are starved. Strix Halo will show what's true.

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OneEng2 said:

Rumor suggests that Strix Halo's 256bit wide DDR 8000 interface is essentially equal to a quad channel memory setup. If true, then such a setup (quad channel moving from DDR6000 to DDR8000) would represent more than enough bandwidth for double the number of Zen 5 cores for Zen 6.

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maddie said:

How does this work with AM5? Already we see Zen5 as having some main memory limitations.

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soresu said:

Can AM5 not use the new CUDIMMs to address that issue?

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poke01 said:

it won’t be AM5 then. AMD needs a new chipset to support CUDIMM, AM5+?

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soresu said:

Chipset and socket are not linked in that way.

As long as the pin configuration is right it's the IMC on the processor package that needs to change to support a variant of DDR5.

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maddie said:

Lets take this a bit further. Would there be frequency limits to the motherboard and its memory trace specifications, even if the raw CPU was capable? Might a 24C Zen 6 be throttled? Lower core counts models should be OK. Not a bad position for those upgrading, if true.

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