Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

DisEnchantment · Apr 24, 2020

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.

N7 performance is more or less understood.

This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

jpiniero · Nov 30, 2024

maddie said:
That's my understanding also. A16 = N2 with BSPD/SPR.

To me it seems more a branding move because TSMC is going to charge a lot more for A16.

maddie · Nov 30, 2024

jpiniero said:
To me it seems more a branding move because TSMC is going to charge a lot more for A16.

Don't you think it will take more fab steps? First you do the power layers and data vias, then the transistors, finishing with the data pathways. I assume the data signals have to pass up through the through the power layers to the data fabric or vice versa. One of them have to pass through the other and assume the power will be the one closer to source.

Previously, you could lay the power and data paths in one set.

oak8292 · Nov 30, 2024

jpiniero said:
To me it seems more a branding move because TSMC is going to charge a lot more for A16.

They have said it costs more and yes it will be more expensive and probably a lot lower volume in wafers. It will be interesting to see if they ever break out revenue for A16 or if it is just included in the N2 revenue.

DrMrLordX · Nov 30, 2024

SiliconFly said:
Ian Cutress asks: "If someone chooses A16 node, do they have to take SPR with it?"

Kevin Zhang replies: "A16 by definition will have BSPD. Yes. But we do allow customer to leverage existing design... ... and they don't have to use BSPDN"

It seems that Zhang here is implying that people who don't want SPR have other nodes (e.g. N2) they can choose from at TSMC.

FlameTail · Nov 30, 2024

DrMrLordX said:
It seems that Zhang here is implying that people who don't want SPR have other nodes (e.g. N2) they can choose from at TSMC.

N2, N2P, N2X.

Plenty of options.

Saylick · Dec 1, 2024

DrMrLordX said:
It seems that Zhang here is implying that people who don't want SPR have other nodes (e.g. N2) they can choose from at TSMC.

FlameTail said:
N2, N2P, N2X.

Plenty of options.

This. TSMC doesn’t force any of their customers into adopting a node with a certain feature because they understand that nothing comes free, so they simply just offer a gamut of choices and let their customer choose what fits their needs. It’s a very customer-focused business model, which is not surprising given that their whole business was to be the world’s first pure play foundry. I’d argue that Intel forcing customers to adopt BSPDN with 18A is less favorable than TSMC’s “offer a variety of options and let the customer choose” approach. That is, if it is Intel’s desire to actually make 18A an external node. Can’t just adopt Henry Ford’s “you can have any color you want as long as its black” mentality if you want to be customer focused, because that just screams “I know what’s right for the customer” which is kind of patronizing.

FlameTail · Dec 1, 2024

Intel 18A uses PowerVia BSPD, which is inferior to the Backside Contact BSPD that is used by TSMC A16.

Slide from:

Clash of the Foundries: Gate All Around + Backside Power at 2nm

Fab Cost, SRAM Scaling, WFE Implications, Backside Power Details, TSMC, Samsung, Intel, Rapidus TSMC won FinFET. All noteworthy leading edge logic designs, even Intel’s, are manufactured on TS…

semianalysis.com

I wonder, when will Intel upgrade to Backside Contact?

dttprofessor · Dec 1, 2024

Saylick said:
This. TSMC doesn’t force any of their customers into adopting a node with a certain feature because they understand that nothing comes free, so they simply just offer a gamut of choices and let their customer choose what fits their needs. It’s a very customer-focused business model, which is not surprising given that their whole business was to be the world’s first pure play foundry. I’d argue that Intel forcing customers to adopt BSPDN with 18A is less favorable than TSMC’s “offer a variety of options and let the customer choose” approach. That is, if it is Intel’s desire to actually make 18A an external node. Can’t just adopt Henry Ford’s “you can have any color you want as long as its black” mentality if you want to be customer focused, because that just screams “I know what’s right for the customer” which is kind of patronizing.

Intel won't force anyone.

Saylick · Dec 1, 2024

dttprofessor said:
Intel won't force anyone.

If by “not force” you mean customers can always choose not to fab at Intel, then sure. But as it stands if you want Intel 18A, it’s going to come with PowerVia whether you want it or not.

JasonLD · Dec 1, 2024

TSMC with competition would have provided BSPD on all of their N2 tier processes without extra cost to its customers. Without competition, TSMC is free to charge even higher price with processes with BSPD.

dttprofessor · Dec 1, 2024

JasonLD said:
TSMC with competition would have provided BSPD on all of their N2 tier processes without extra cost to its customers. Without competition, TSMC is free to charge even higher price with processes with BSPD.

$30k

RTX · Dec 1, 2024

FlameTail said:
Intel 18A uses PowerVia BSPD, which is inferior to the Backside Contact BSPD that is used by TSMC A16.

I wonder, when will Intel upgrade to Backside Contact?

Probably when they do CFET. All 3 foundries will have to do both for CFET.

Saylick · Dec 1, 2024

JasonLD said:
TSMC with competition would have provided BSPD on all of their N2 tier processes without extra cost to its customers. Without competition, TSMC is free to charge even higher price with processes with BSPD.

I hear ya, but without knowing what 18A costs relative to N2 and A16 it’s hard to provide evidence for this claim. If you know the prices, please share.

RTX · Dec 1, 2024

Saylick said:
I hear ya, but without knowing what 18A costs relative to N2 and A16 it’s hard to provide evidence for this claim. If you know the prices, please share.

PowerVia lets Intel not aggressively scale down the pitches.

OneEng2 · Dec 1, 2024

oak8292 said:
From Ian’s interview.

“Q: So if somebody chooses the A16 node, do they have to take the Super Power Rail with it?

A: A16 by definition will have Super Power Rail, yes.”

I think the confusion is whether A16 is a variant of N2 or a new node. From what I read A16 is a high cost variant of N2 for HPC and AI. The optionality of not using SPR is to stay with the lower cost N2 and the expectation is that smartphone die which are cost sensitive and lower power will not move to A16. These nodes will be made in the same fab with the same equipment.

The ‘mobile’ term incorporating both laptops and smartphones is problematic. A PC laptop may operate at 35 watts with higher short term bursts. This doesn’t really work on smartphones.

In my mind one of Intel’s big issues is that their process design is focused on the PC market which has been essentially stagnant for 10 years. PCs peaked at 400 million per year back in the netbook days, pre tablets.

‘Mobile’ or smartphones with power budgets below 10 watts grew to billions per year with small dense die that run at lower frequencies on lower cost processes.

Possibly. Their current processor design also seems better suited to consumer applications than DC as well. This could be problematic from a revenue perspective.

ajsdkflsdjfio said:
I agree, mobile smartphones and laptops are completely different classes of products akin to laptop vs desktop. It's pretty clear TSMC will still be the breadwinner for the extreme mobile segment (smartphones, tablets etc), but I think the fact that intel is now using their new 18a node for panther lake, a mobile ultrabook oriented product, instead of TSMC N3B like for lunar lake is a good sign that intel is making headway towards not just higher performance but also density and ppw in their node offerings. Besides, data center is now the new growing segment and I think there is a strong case for 18a's use in data center. Minus the heat complications of powervia, all of intel's new technologies(ribbonfet powervia) provide better transistor density and ppw which are key to data center applications.

High density and low power will work great for everything except HPC. Just as AMD has partitioned it's DC product lines, perhaps Intel will as well?

maddie said:
Don't you think it will take more fab steps? First you do the power layers and data vias, then the transistors, finishing with the data pathways. I assume the data signals have to pass up through the through the power layers to the data fabric or vice versa. One of them have to pass through the other and assume the power will be the one closer to source.

Previously, you could lay the power and data paths in one set.

I agree. It will be a more expensive process.

DrMrLordX said:
It seems that Zhang here is implying that people who don't want SPR have other nodes (e.g. N2) they can choose from at TSMC.

That was what I inferred as well.

Saylick · Dec 1, 2024

RTX said:
PowerVia lets Intel not aggressively scale down the pitches.

View attachment 112430 View attachment 112431

That I can understand, but from what I recall the overall fabrication process to implement any form of BSPD requires additional steps. Not sure how many steps this adds and how much extra it costs, however.

ajsdkflsdjfio · Dec 1, 2024

Saylick said:
But as it stands if you want Intel 18A, it’s going to come with PowerVia whether you want it or not.

Where is this coming from, I'm not entirely sure since it's really hard to find information about this, but what little information I did find on the optionality of powervia on 18a seems to indicate customers can choose to produce chips on 18a without powervia.

It may well be the case that 18a is powervia only, but I fail to find any concrete information on that being true or not.

Saylick · Dec 1, 2024

ajsdkflsdjfio said:
Where is this coming from, I'm not entirely sure since it's really hard to find information about this, but what little information I did find on the optionality of powervia on 18a seems to indicate customers can choose to produce chips on 18a without powervia.
View attachment 112439 View attachment 112440
It may well be the case that 18a is powervia only, but I fail to find any concrete information on that being true or not.

I don’t have a definitive source, but every indication I’ve seen, including reading Intel PR statements, suggests that PowerVia is tied to 18A. PowerVia allows Intel to relax the pitch of the front side interconnect, so I surmise if there was some optionality to PowerVia, 18A would recess on density and thus no longer be the same node. Conversely, TSMC’s N2 and A16 appear to be sister nodes designed using the same pitch, which allows for the optionality of backside direct contact.

Regarding 18A:

Intel's recent research is shaping the future of transistor technology. By advancing 3D stacked CMOS transistors and backside power delivery methods like PowerVia, Intel is extending Moore’s Law well beyond current expectations. These innovations, closely tied to Intel 18A, are driving improvements in transistor density and power efficiency, ensuring Intel stays competitive in the high-performance computing space.

Source: https://semiwiki.com/forum/index.ph...ed-how-ribbonfet-boosts-ai-scalability.21352/

Regarding N2 vs. A16:

Their implementation of backside contacts appears to be conservative in its 1st generation. A claimed 7-10% density increase is roughly half of what’s possible from cell scaling in theory. This is probably done to maintain design compatibility with N2, likely the FEOL will stay the same and only routing must be redone to utilize the backside power network. IR drop is also significantly reduced with up to 20% power improvement possible.

Source: https://semianalysis.com/2024/10/01/clash-of-the-foundries/

OneEng2 · Dec 1, 2024

Based on the prices I see for TSMC N2 wafers (in excess of 30K per wafer vs 18,500 for N3), I suspect that Intel's 18A is even MORE expensive as it not only uses GAA, it also uses BSPD. AFAIK both are using ASML’s NXE 3000 series EUV scanners (.33) vs the high NA 5000 series.

Seems pretty obvious to me that the cost of ATTEMPTING to keep up with Moore's law and continuing the business models of decades past has greatly exceeded the consumers desire to pay for it. What I mean here is that from N5 to N2 cost have doubled per wafer. It seems pretty clear that desktop and laptop prices can NOT double as the market will not bear such an increase.

AMD's practice of staying off the leading node for everything but data center tiles (where the market will actually pay for it .... for now) has been working for them, but as the "next new old node" costs ALSO skyrocket, I think even this will have to end.

So the death of Moore's law won't be caused by physics, but rather by economics.

Doug S · Dec 1, 2024

I already replied to you in another thread, but it has long been known that Moore's Law would end due to economics. I think you are underestimating when that will happen. It won't be in the next couple decades, IMHO.

SiliconFly · Dec 2, 2024

Doug S said:
I already replied to you in another thread, but it has long been known that Moore's Law would end due to economics. I think you are underestimating when that will happen. It won't be in the next couple decades, IMHO.

Moore's Law can't or won't end now (or anytime in the future). It's been more than a decade since Moore's Law has slowed down. This slow down/deviation indicates that Moore's Law is already broken.

igor_kavinski · Dec 2, 2024

Sigh. It was never a law to begin with. It was an observation and it hasn't been very relevant for a long time now. Moore is gone. Let his "law" go too. Let it go, people!

NostaSeronx · Dec 3, 2024

Dennard Scaling is probably more important than Moore Scaling.

FDSOI CMOS with dual backgate control for performance and power modulation, 2009, https://ieeexplore.ieee.org/document/5159302/
to
Unlimited Bi-directional Back-Bias in FD-SOI Technology With New Dual Isolation Integration, 2024, https://ieeexplore.ieee.org/document/10631338

Then, there is the domino circuit stuff: https://ieeexplore.ieee.org/document/10106142
"Nontraditional Design of Dynamic Logics Using FDSOI for Ultra-Efficient Computing"

Die #1 something like this: FD-SOI BiCMOS for logic
Die #2/#3 would be; standard FD-SOI for SRAM/eSRAM
Boom, the gov can revive the Ultra High Clock Rate Computing(single core @ >32 GHz, OHPC -> UHPC) project from 2010. Since, that can't be done on FinFETs/GAAFETs since they abandoned Dennard Scaling.

Picture for the single-core 130nm BiCMOS -> 90nm BiCMOS product. Given bulk for 45nm PDSOI and 22nm FDSOI: https://ieeexplore.ieee.org/document/10732195 , with this being pushed to 12FDX from the Europe R&D. Which might rather use lateral BiCMOS on SOI (full SOI integration rather than Bulk-side) for the >1 THz Fmax/>700 GHz Ft grouping. Which is done by the US R&D side. STM-version: 'This work, for the first time, demonstrates an oscillation frequency fmax of 2.7 THz achievable by tuning the substrate bias in an asymmetric silicon-on-insulator (SOI) lateral SiGe HBT.' Regardless, yum bipolar digital applications.

All this bleeding/leading edge stuff with thems larger transistors. Has gone and really pushed the industry in a pickle.

Doug S · Dec 3, 2024

Didn't they go to "thems larger transistors" because of power? 32 GHz sounds great until you calculate how much power it will draw.

RTX · Dec 3, 2024

https://www.eetimes.com/finfets-fd-soi-proposition-may-save-power/

FDSOI Finfet is around the same as Bulk Finfet cost

Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

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