Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

DisEnchantment · Apr 24, 2020

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.

N7 performance is more or less understood.

This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

SiliconFly · Dec 7, 2024

Pat Gelsinger owned it today! And it was savage!

Dunno who that poor guy is, but I don't think he's gonna recover from this for a while.

Thibsie · Dec 7, 2024

Savage ? It's just basics.
One is indeed clueless but there's nothing savage here. What about some objectivity, huh ?

SiliconFly · Dec 7, 2024

Thibsie said:
Savage ? It's just basics.
One is indeed clueless but there's nothing savage here. What about some objectivity, huh ?

Oh pls. It's just basics. But it's the way he delivered it in a public forum. Very unlike him. And you just couldn't see that.

Win2012R2 · Dec 7, 2024

Pat has got a lot of time on his hands now and I have heard on good authority that he will start posting on here any minute now...

DrMrLordX · Dec 7, 2024

Win2012R2 said:
Pat has got a lot of time on his hands now and I have heard on good authority that he will start posting on here any minute now...

Will he do any pushups for us?

name99 · Dec 7, 2024

SiliconFly said:
Pat Gelsinger owned it today! And it was savage!

View attachment 112817

Dunno who that poor guy is, but I don't think he's gonna recover from this for a while.

Both are being dumb!

In the case of the TSMC N2 report or the Intel 18A report, obviously the numbers (10% or 60%) refer to some sort of test chip.
What is that test chip? We have no idea. it could be basically an SRAM vehicle. It could be a simple ARM chip. It could the Apple A18 for TSMC. It could be Panther Lake for Intel. Who knows?

The exact number is not especially interesting or important bcs we don't know the chip it's relative to. What's more interesting (assuming truth in both cases...) is that the Intel leaker is trying to say "things are bad, man" while the TSMC leaker is trying to say "thing are on track, exactly as expected".

SiliconFly · Dec 7, 2024

name99 said:
Both are being dumb!

In the case of the TSMC N2 report or the Intel 18A report, obviously the numbers (10% or 60%) refer to some sort of test chip.
What is that test chip? We have no idea. it could be basically an SRAM vehicle. It could be a simple ARM chip. It could the Apple A18 for TSMC. It could be Panther Lake for Intel. Who knows?

The exact number is not especially interesting or important bcs we don't know the chip it's relative to. What's more interesting (assuming truth in both cases...) is that the Intel leaker is trying to say "things are bad, man" while the TSMC leaker is trying to say "thing are on track, exactly as expected".

Nope. Try reading the entire convo in the last 48 hrs. What they're saying is, both 18A & N2 are pretty much on track.

adroc_thurston · Dec 7, 2024

https://twitter.com/x/status/1865524227702698387

Oooh yeah baby pump CFETs right into my veins

NostaSeronx · Dec 7, 2024

adroc_thurston said:
Oooh yeah baby pump CFETs right into my veins

Technically, GlobalFoundries is sitting on its 12XP-3D process. Replaces the variable-doped SiGe/Si single-work function for a undoped Si multi-work function. With a yield improving 3rd gen RIE, so transistors going from 12LP to 12XP will have a different Fin shape again(like 14LPP -> 12LP).

4-Fin in folded config = 6T and stitched config = 5.5T with the above process. There is more improvement with 8T SRAMs than 6T SRAMs.

OneEng2 · Dec 7, 2024

SiliconFly said:
In a surprising turn of events, Pat Gelsinger has finally spoken. Replying to Patrick Moorhead, he confirms that the 18A 10% yield leak is in fact fake news.

That isn't what he said (or at least how I read it).

Pat pointed out (correctly) that Yield is a poor metric, since the same defect density will have different yields on different sizes of die. Larger die will always have lower yields as the probability that a defect will exists will be higher than on a smaller die for the same defect density.

Another point is the type of logic gates being yielded. Some are quite easy to yield high and others quite difficult. The mix of different types of gates in the design makes a big difference to how well the process will actually yield at the end of the day.

What Pat did NOT say, was that the 10% number wouldn't be CORRECT on some size die of some type of logic.

Again, my feeling is that 18A is very likely having issues simply because Intel hasn't come out with some solid metrics related to yield to dispute the rumors. All we have from Intel is "fluffy bunny" and "feel good" statements. Nothing solid.

Granted, TSMC's N2 metrics have been less than complete; however, they have stated they were getting >80% yield on 256Mbit SRAM (which is at least a solid metric for that application). Furthermore, TSMC isn't planning N2 HVM until Q4 2025. Intel, on the other hand, is planning on Panther Lake in "Mid 2025" which sound pretty sketchy to me, considering the lack of information we are seeing on 18A currently.

In all fairness, if TSMC isn't showing solid metrics on N2 by May 2025, then I'll be the first one to start doubting their Q4 targets as well. The current trickle of metrics from TSMC's N2 seem favorable to a Q4 2025 launch while the current trickle of metrics from 18A do not seem favorable to a "Mid 2025" Panther Lake launch.

OneEng2 · Dec 7, 2024

Ok, did some more digging.

Using semianalysis.com yield calculator and Panther Lake dimensions of 8mmx14.288 and Intel's reported "D0 < 0.4" (say .36) for 18A you get a yield of 65%.

Using the largest die the equipment can make "Retile Limit" 26mmx33mm you get 7.95% which is <10% .... but meaningless since no one makes a tile that big .... for obvious reasons .

Now, we can argue about the believability of Intel's reported D0 < 0.4, but if we are to believe it, then the yield for Panther Lake at least isn't in the realm of "God Awful".

Still, the Broadcom rumor isn't instilling any confidence.

RTX · Dec 8, 2024

NostaSeronx said:
Technically, GlobalFoundries is sitting on its 12XP-3D process. Replaces the variable-doped SiGe/Si single-work function for a undoped Si multi-work function. With a yield improving 3rd gen RIE, so transistors going from 12LP to 12XP will have a different Fin shape again(like 14LPP -> 12LP).
View attachment 112841
4-Fin in folded config = 6T and stitched config = 5.5T with the above process. There is more improvement with 8T SRAMs than 6T SRAMs.

Stacked planar transistors with only front side power?

NostaSeronx · Dec 8, 2024

RTX said:
Stacked planar transistors with only front side power?

Complementary-stacked FinFETs with only front-side power. Which should be part of the backport of FX-7's CoolCube that was in it's roadmap.

I think these numbers for the old 12FDX and 14LPP with a CoolCube module still apply for masks and costs;
12FDX (old) = 53 masks, $3900 USD
12FDX+CC = 68 masks, $5500 USD
14LPP (old) = 63 masks, $5000 USD
14LPP+CC = 83 masks, $7000 USD
Not sure the above is transistor-level but rather IP-level. Scanning through the documents it is likely Memory on Logic.
Memory on Logic = 1000-nm distance
1st Gen PFET~NFET = 300-nm distance
2nd Gen PFET~NFET = 100-nm distance

AMD has already done 88mask+88mask so standard 3d stacking should still work, it is not removed. Which means further More than Moore shrinks could be achieved.

Modern S3D/M3D/CoolCube 12XP shrink-wise should be close to 0.52x compared to a theoretical FX-7 at 0.49x. FX-14 9-track/4-fin to FX-7 9-track/4-fin ~= 12XP-3d 6-track/4-fin

SiliconFly · Dec 8, 2024

OneEng2 said:
Using semianalysis.com yield calculator and Panther Lake dimensions of 8mmx14.288 and Intel's reported "D0 < 0.4" (say .36) for 18A you get a yield of 65%.

Finally! But these D0 numbers are months old. Yield should be higher now. Probably around ~70%.

OneEng2 said:
Using the largest die the equipment can make "Retile Limit" 26mmx33mm you get 7.95% which is <10% .... but meaningless since no one makes a tile that big .... for obvious reasons .

Very true (and I assume you mean Reticle Limit).

OneEng2 said:
Now, we can argue about the believability of Intel's reported D0 < 0.4, but if we are to believe it, then the yield for Panther Lake at least isn't in the realm of "God Awful".

Still, the Broadcom rumor isn't instilling any confidence.

I think the most important thing to worry about is volume. When TSMC say it's ready to manufacture, they always hit volume on time. But when Intel says the same, they mean something else and aren't able to ramp up on time. I don't think it's incompetency, more like Intel has execution issues.

SpudLobby · Dec 8, 2024

jdubs03 said:
Ah yeah true. Not happening then.

Yeah there is 0 chance they will use N2 2025. And I get it, doesn’t make sense.

igor_kavinski · Dec 8, 2024

SiliconFly said:
But when Intel says the same, they mean something else and aren't able to ramp up on time. I don't think it's incompetency, more like Intel has execution issues.

If they ever have stable foundry customers in future, they won't be able to do that anymore because it would be akin to screwing over their customers.

Aapje · Dec 8, 2024

adroc_thurston said:
https://twitter.com/x/status/1865524227702698387
Oooh yeah baby pump CFETs right into my veins

CFET is 2030+ technology though, so it will take a while.

bearmoo · Dec 8, 2024

Aapje said:
CFET is 2030+ technology though, so it will take a while.

Ian used to do good work back in the Anadtech days. Nowadays it's more like PR.

SiliconFly · Dec 8, 2024

bearmoo said:
Ian used to do good work back in the Anadtech days. Nowadays it's more like PR.

Cos he said some interesting things about IFS? 🤦‍♂️ I think he knows his stuff and knows more insiders than most.

jur · Dec 8, 2024

OneEng2 said:
Granted, TSMC's N2 metrics have been less than complete; however, they have stated they were getting >80% yield on 256Mbit SRAM (which is at least a solid metric for that application). Furthermore, TSMC isn't planning N2 HVM until Q4 2025. Intel, on the other hand, is planning on Panther Lake in "Mid 2025" which sound pretty sketchy to me, considering the lack of information we are seeing on 18A currently.

256 Mbit SRAM chip has die size of approx. 7mm^2 (TSMC N2 SRAM density). To get 80% yield one needs defect density less than 3 defects / cm^2, so this really tells us nothing, except that the process probably isn't totally broken.

Win2012R2 · Dec 8, 2024

jur said:
this really tells us nothing

To us, but a LOT to those who have full details, ie Apple/AMD/NVIDIA.

I believe it's the usual first SRAM TSMC is doing, so comparing it with their historical node dev can give pretty good idea how well new process is going, especially important in light of new information that SRAM density on N2 will finally go up again.

reaperrr3 · Dec 8, 2024

SiliconFly said:
Finally! But these D0 numbers are months old. Yield should be higher now. Probably around ~70%.

Maybe, but yield improvements aren't just steadily happening automatically, but rather the result of changes, and in some cases probably with some trial and error involved.
One issue that seems to have been plagueing both Samsung and Intel for the last couple of years is that they were at times bashing their heads against walls with little to no progress.

I don't remember where I heard/read it, so take it with a spoon of salt, but I remember talk about that at one point there was a phase of almost no notable progress on Intels 7nm EUV (what's now known as Intel 4/3) production readiness for nearly an entire year during the Swan / Murthy era.

RTX · Dec 8, 2024

NostaSeronx said:
Technically, GlobalFoundries is sitting on its 12XP-3D process. Replaces the variable-doped SiGe/Si single-work function for a undoped Si multi-work function. With a yield improving 3rd gen RIE, so transistors going from 12LP to 12XP will have a different Fin shape again(like 14LPP -> 12LP).
View attachment 112841
4-Fin in folded config = 6T and stitched config = 5.5T with the above process. There is more improvement with 8T SRAMs than 6T SRAMs.

CoolCube already had 100 million vias in 2013/2015 time frame. Any more updates on that?

Win2012R2 · Dec 8, 2024

igor_kavinski said:
they won't be able to do that anymore because it would be akin to screwing over their customers

Like Altera?

igor_kavinski · Dec 8, 2024

Win2012R2 said:
Like Altera?

That's their own company, isn't it? They have license to screw their own

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