Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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fastandfurious6

Senior member
Jun 1, 2024
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looks disappointing if true but scores should be much higher, it's x16 zen5 + double bandwidth

r23 score is same as zen 4 7945hx - maybe the efficiency in 90w shown vs 140w+ ? but it plateaus at 90w

timespy, 7735hs is zen 3... at 70w it's 8000 vs 9000 only?
 

MS_AT

Senior member
Jul 15, 2024
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Strix halo looking good
Could you link the source?

looks disappointing if true but scores should be much higher, it's x16 zen5 + double bandwidth
Here we go again, could you show R23 scaling with memory bandwidth?
R23 is only ~33000, should be higher closer to 9950x score
And have you measured how well 9950x scores in the 13inch tablet with tons of Asus bloatware installed and pre-release firmware limited to 80W?
 

Det0x

Golden Member
Sep 11, 2014
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AMD have gotten their own APO it seems




Wonder what programs is supported and how it affects performance..
New chipset driver is recommened for the newest ageasa
hey guys agesa 1203 bios solve unknown device problem
just need install new chipset driver

AMD chipset driver 7.01.08.129
*Improves performance for 2CCD Raphael and Granite Ridge CPUs
 

fastandfurious6

Senior member
Jun 1, 2024
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And have you measured how well 9950x scores in the 13inch tablet with tons of Asus bloatware installed and pre-release firmware limited to 80W?

you might be right about that. super impressive they put a whole 9950x + 4060 in a goddamn tablet

my comment was about the plateau on the graph but the graph is just bad
 

CouncilorIrissa

Senior member
Jul 28, 2023
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No power, same high bandwidth, 32 bytes per cycle in both directions, lower latency.
So unless the interconnect clocks massively higher, the read throughput from IOD to CCD remains the same as on GNR.
UPD: oh they're clocking the IF in-between 1-2 GHz.
 
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branch_suggestion

Senior member
Aug 4, 2023
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So unless the interconnect clocks massively higher, the read throughput from IOD to CCD remains the same as on GNR.
2/3 benefits already met, the last can be saved for Medusa, plus they can juice the clocks for the given platform.
It is a proof on concept pipe cleaner after all, don't want to do too much modding.
 

MS_AT

Senior member
Jul 15, 2024
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So unless the interconnect clocks massively higher, the read throughput from IOD to CCD remains the same as on GNR.
UPD: oh they're clocking the IF in-between 1-2 GHz.
So as always after AMD interview a guessing game begins. What is the actual CCD to IOD connection speed.

In Granite Ridge we have 32B read and 16B write. (https://chipsandcheese.com/p/amds-turin-5th-gen-epyc-launched)
In Turin we have 32B read and 32B write (https://chipsandcheese.com/p/amds-turin-5th-gen-epyc-launched)
In Halo apparently also 32B and 32B write but quoting the interview
So the first big change between a Granite or a 9950X3D and this the Strix Halo always the die to die interconnect. Low power, same high bandwidth, 32 bytes per cycle in both directions, lower latency.
It might be a transcript issue, he might have misspoken, or it might be another case of "two decoders are able to work on 1T instruction stream" case

Still if the statement is accurate then they did double the bandwidth, just the write bandwidth compared to desktop zen5

Also I was surprised that GMI physical is clocked at 20GHz and I am not sure how it works exactly if the clocks reported by software show 2GHz.
We are able to get power benefits. Because prior to that, we had a GMI PHY that lived in there and that consumed a whole lot of power in order to be able to send this over high frequencies over short distances. Here we are clocking it at a way less than the 20 gigs that the GMI was being clocked at.
 

eek2121

Diamond Member
Aug 2, 2005
3,202
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2 x USB4 + other gen 3 and 2.
16 PCIe lanes.

You can have an x8 to an external GPU + 2xSSD, or 4x to an I/O hub, 8x to a GPU, and 1xssd, or 4xssd, or a few thunderbolt ports and a couple SSDs.
Why would you use a GPU with this part outside of eventual upgrades (when games become too demanding to run, which won’t happen for a long time)
Except they will pair it with crappy LPDDR5. Mendocino has 5500 MT/s and it's almost atrocious.
Meh, bandwidth is fine.
How about +100 or +150?
My 7950x won’t do +50 even. It jumps off the motherboard and runs away if I even think about enabling PBO.
And this at the end:

Overall, other aspects remain mostly unchanged but there is a high probability that AMD's Ryzen sales could overtake Intel this quarter. Budget Ryzen 9000 non-X CPUs will go neck and neck against Arrow Lake non-K, though AMD has a clear platform advantage.
Fallen, Intel has.
In the notes it says Asus TUF A16 Advantage Edition, so it could be a Radeon 7600S or a 7700S, difficult to judge because it seems not set at max TDP.
Ignore early benchmarks, and ignore benchmarks from a single product. Consider it a ballpark.
AMD have gotten their own APO it seems
View attachment 114842

View attachment 114843

Wonder what programs is supported and how it affects performance..
New chipset driver is recommened for the newest ageasa
Sadly, best ASUS has given me is AGESA 1.2.0.2b
I haven't finished watching the interview at the time I posted this and was hoping that they'd at least clock it higher with STXH, but no.

So yeah, we're stuck with 64 GB/s read bw per CCD.
Lame
Classic AMD - the cheapo company.
They have to save some gains for next gen. 🤣

They never know if Intel might pull another Core(tm) moment.

Cheers🥂
 

CouncilorIrissa

Senior member
Jul 28, 2023
602
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It might be a transcript issue, he might have misspoken, or it might be another case of "two decoders are able to work on 1T instruction stream" case
Not a transcript issue, that's exactly what he said. 3:36

I think he simply misspoke and meant that 32B/cycle behavior is similar to that of Strix Point.
 
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