Die to die connection changes require a new die. This is done for low power, who here is disputing that? Its a new low power core option. You want low power cores, you need that different CCD and die to die connection. Its not mentioned, but probable, that the die to IOD connections differ as well, designed for power savings.Even without the typo it was clear by the surrounding context they were talking about the d2d connection, but it’s good that the correct transcript says it outright.
No, they do not. They just require that the CCD features both interfaces. Same as MI300A, same as X3D, they all use the same CCDs as the vanilla products.Die to die connection changes require a new die.
No. GMI is uncore.Its a new low power core option.
Per-core power is "low" in several Turin SKUs as well.I still maintain that the roadmap is referring to the Strix Halo cores, as they are not C cores, yet can operate at much lower power than standard cores.
PS: Different bins though, and possibly different steppings.they all use the same CCDs as the vanilla products.
Yeah times perfectly.No way this is N2P/x those are entering HVM in 2026
Just don't.Wont be N2 unless its still 3 years out. N3P is possible, but so is N3E. Either way, max frequencies arent going up, and it will bring a ~10% IPC uplift
Bruhhhhh you don't understand the time HVM entering in H2 26 means products launch Q2 27 at the earliest Zen6 is H2 26 launchYeah times perfectly.
I kinda agree, but at the same time we have to consider the current AMD is very different from the AMD that developed zen 1 to zen 4. Around the time they started working on Halo, they had probably realized they weren't a broke company without profits anymore, and their products were going to beat Intel ones for a long time.We're talking about AMD here. They're the last company in the industry to tape out another core design for the product lineup that's going to appear in 10 low-volume SKUs at most, on client no less.
It would be extremely uncharacteristic of them.
loud incorrect buzzer noisethey all use the same CCDs as the vanilla products.
N2 got pulled in. Next.Bruhhhhh you don't understand the time HVM entering in H2 26 means products launch Q2 27 at the earliest Zen6 is H2 26 launch
No, Halo has unique CCDs.No, they do not. They just require that the CCD features both interfaces. Same as MI300A, same as X3D, they all use the same CCDs as the vanilla products.
More differences than just another stepping?Desktop and server do not share the CCD, just the design itself.
But non-portable computers will be mostly relegated to workstations, either compact desktops, or HEDT like, and DIY gaming enthusiasts.These fantasies that non-portable computers will eventually be replaced by portable ones are complete nonsense.
– Ergonomics,
– potential computing capacity,
– economics
of portable computers are drastically inferior to non-portable ones.
Yeah, very very different xtor-level optimizations.More differences than just another stepping?
Nope, just a test véhicule for Zen6.I honestly don't believe the rumors, or, if they did make a new die just for strix halo, then that guarantees a Zen 5+ release at some point. Literally they would have been better off making strix halo monolithic if the CCDs aren't being used anywhere else. Makes zero sense. Also a lot of money to waste on extra validation, extra silicon and substate operations, ect.
Absolutely nobody have said anything about scaling Andoid Apps to Windows.
I was talking, for very reasons you mentioned, about scaling Android OS to desktop and laptop form factors.
Vertical integration of Android ecosystem with ARM chips becomes absolutely possible now.
My uninformed guess, would be that they are using "sea of wires" for a reason and that reason is they have changed from "more serial" physical interconnect clocked at 20sth GHz to a "more parallel" one they can clock at 2 GHz. Since they maintain BW, that means they have ~roughly 10 times more wires, meaning more contacts on the CCD itself. Since IO takes space might be they have done some frequency space trade-off on rest of the chip to accommodate more IO and keep sensible v/f curve, since Halo is limited to 5.1GHz boost.If its just a different GMI interconnect, why isn't there a chance its already on all the normal CCDs? It could have a legacy mode for the old desktop IO die, and the new mode for higher spec controllers.
AMD says a special edition 9950x3d with both CCDs having Vcache might come to be, but not likely.
We could make a Ryzen 9 9950X3D with 3D V-cache on all 16 cores, AMD tells us
AMD confirms that it could make a limited edition dual-CCD Ryzen X3D gaming CPU with 3D V-cache on both CCDs, but it would be a niche product.www.pcgamesn.com
It would calm some people's OCD.Not surprising. Surely AMD has samples and knows the numbers. I don't know why there are armchair CPU designers out there who think they know better.
Obessive CCX Disorder?It would calm some people's OCD.
Obsessive Cache DisorderObessive CCX Disorder?
Well, it is surprising. What is the investment needed for introducing such dual-CCD SKU? What else on top of proper binning and producing a fw revision is required?Not surprising. Surely AMD has samples and knows the numbers. I don't know why there are armchair CPU designers out there who think they know better.