Question Question about PCIe versions and slots and lanes - please spoonfeed me.

So, the CPU and MOBO chipset dictate how many devices you'll be able to use. As it sits today you get 16x for the top slot + 4x for the first NVME. 20 lanes chews up quite a bit already and then you also have x4 going to the chipset devices. Now you're down to 4x.

It's now a game of planning on which card goes where and how high of a priority you place on its bandwidth. Most of he 870 boards now give us 3 slots to play with and should be sufficient for most of us. I just picked up a board with the intent of killing off a TBT card in the process by moving the ports to the USB4 on the IO backplate. Leaves me 3 slots.. GPU/X550/OTA card. If I need an extra slot I can pull the OTA card and use the external tuner instead.

It's all just a matter of math. The chipset is how you get around the cap but sacrifice full bandwidth for the additional devices.

boed said:

I still after years don't really understand pcie lanes and slots. I'm curious about how cards work when they need to share and there is a limit to how many lanes are available. While I know this will work, I'm curious about latency, lane switching, PCIe 3.0 in 5.0 slots - does it use less lanes etc.

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The answer to the last question is no. The maximum number of lanes that a PCIe card (or m.2 slot) actually uses is hardwired. Any PCIe card can run at a slower speed (PCIe version) than what the slots supply, but they can't go faster. Also, any card should be able to use fewer lanes than the card's hardwired maximum, but it can't use more. (So if you put an x16 GPU into a slot that's physically x16 but electrically x4, the card will work and use 4 lanes. If you put a card like an RX6400 that electrically uses 4 lanes into a slot wired for x16, the card still only uses 4 lanes.)

On the slot side of things, there are a couple ways that the mobo designer can go. The easiest is that the number of electrical lanes for each slot is fixed and hardwired. (As noted above, a slot can be larger physically than it is electrically.) A common variation is that if you have more devices attached than total lanes available, some slot(s) are disabled; an example would be slot #x is disabled if you put an NVMe drive into m.2 slot #y. (The choice of which slots are disabled by what is chosen by the motherboard designer and is hardwired in.) The second option is called bifurcation, whereby the board decides to share some lanes across slots instead of connecting them all to one slot. The usual setup is an x16 slot being reduced to x8 when another slot is populated, with the second slot also getting x8. The lane redistribution is fixed, in the sense that your options are x16+x0 or x8+x8, and nothing else; you generally can't ask for x8+x4+x2+x1 or some other arbitrary lane distribution.

There's actually a third option which I've never seen built in, which is a PCIe switch. A switch works sort of like the chipset (more precisely, the chipset will incorporate a PCIe switch as part of its capability). It generates new PCIe lanes out of thin air, with the caveat of course being that ultimately the total bandwidth available across all the new lanes isn't any more than the bandwidth going into the switch. You'll see switches on some multiple drive m.2 cards. A switch is a relatively expensive chip, so it's rarely or never seen on the motherboard itself outside of the one built into the chipset.

Does that help any?