Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

João Bortolace · Jan 31, 2025

Kepler_L2 said:
And I struggle to see how Intel plans to double core counts at any reasonable TDP.

RTX 5090 has 600W TDP, nobody cares about TDP in this segment

igor_kavinski · Jan 31, 2025

It's gonna be a HUGE socket. Maybe 2000+ pins now.

I hope they give at least NVL-S to Z890 owners for their loyalty.

Kepler_L2 · Jan 31, 2025

João Bortolace said:
RTX 5090 has 600W TDP, nobody cares about TDP in this segment

There isn't any desktop socket sized cooler that can handle anywhere near 600W.

Geddagod · Jan 31, 2025

Kepler_L2 said:
There isn't any desktop socket sized cooler that can handle anywhere near 600W.

Or maybe Intel could just not have this sku have the all core turbo pretty much at every cores Fmax this time around. Even iso power it's going to be a huge nT perf improvement, even if it's not 2x.

OneEng2 · Jan 31, 2025

511 said:
Yeah but he is the president of US so even things like that are scary for companies that is why even bluff works

cannedlake240 said:
Lol 2025 was supposed to be THE year Intel returns to form with Diamond Rapids, Falcon, 18A and Nova Lake. I guess in hindsight there was no way they were going to accomplish all that. Now the next estimate for recovery is 2029 at best, after four years Intel is back at square one. DCAI(both traditional & AI) is in shambles, no major foundry clients, maybe NVL will be another "Alder lake moment" or similar

Geddagod said:
I struggle to see how AMD can compete with Zen 6 now in nT at least. Idk how important that will be for them, considering I fully expect them to have the gaming crown by a decent margin, but still.

Kepler_L2 said:
And I struggle to see how Intel plans to double core counts at any reasonable TDP.

I struggle to see how Intel plans to get any kind of decent yield with pie plate sized die (if they indeed plan as in the above link)

It's almost as if Intel can't understand that it ISN'T enough to make the most performant processor in a market segment ..... they have to MAKE MONEY doing it.

Yields and efficiency are critically important. Intel has spent enough money to purchase a US Ford class air craft carrier on 18A R&D to date. If their plan is to make a relatively small number of units at low yield on 18A for a couple of years and then spend ANOTHER 20Bn to develop the next process node .... I don't see the math!

511 · Jan 31, 2025

OneEng2 said:
I struggle to see how Intel plans to get any kind of decent yield with pie plate sized die (if they indeed plan as in the above link)

It's almost as if Intel can't understand that it ISN'T enough to make the most performant processor in a market segment ..... they have to MAKE MONEY doing it.

Yields and efficiency are critically important. Intel has spent enough money to purchase a US Ford class air craft carrier on 18A R&D to date. If their plan is to make a relatively small number of units at low yield on 18A for a couple of years and then spend ANOTHER 20Bn to develop the next process node .... I don't see the math!

They should have figured out something they are using HB with Intel 3/18A/TSMC for NVL

Geddagod · Jan 31, 2025

OneEng2 said:
I struggle to see how Intel plans to get any kind of decent yield with pie plate sized die (if they indeed plan as in the above link)

The rumor is 2x 8+16 dies. Not one large one. Even if Intel was to do that, which is not the rumor, I doubt a 16+32 would be much larger than 200mm2, if that. Which is still large mind you, but no where near so large that yields start becoming a massive issue.

OneEng2 said:
It's almost as if Intel can't understand that it ISN'T enough to make the most performant processor in a market segment ..... they have to MAKE MONEY doing it

E-cores, canning the rumored 8+32 ARL die, canning a bunch of Halo skus, I would imagine are all responses to cost cutting. I think Intel is becoming very cognizant of the fact that they have to cut costs.

OneEng2 said:
Intel has spent enough money to purchase a US Ford class air craft carrier on 18A R&D to date.

LOL that's so funny

Geddagod · Jan 31, 2025

511 said:
They should have figured out something they are using HB with Intel 3/18A/TSMC for NVL

HB?

Geddagod · Jan 31, 2025

igor_kavinski said:
It's gonna be a HUGE socket. Maybe 2000+ pins now.

I hope they give at least NVL-S to Z890 owners for their loyalty.

I wonder if NVL's new platform may have some high end DDR6 boards, kinda like ADL supporting both ddr4 and ddr5 depending on the mobo. I have no clue, I'll admit I don't follow memory tech much at all.
I mean, wouldn't such a massive core count CPU also require equally massive amounts of memory bandwidth?

511 · Jan 31, 2025

Geddagod said:
HB?

Hybrid Bonding 😅 also I think 8+16 will be around 100mm2

Geddagod · Jan 31, 2025

511 said:
Hybrid Bonding 😅 also I think 8+16 will be around 100mm2

Ah I'm dumb, HB being hybrid bonding makes sense lol.
Yea, I agree, one 8x16 die will prob would be ~100mm2. ARL's die is around the same size IIRC.

MS_AT · Jan 31, 2025

Kepler_L2 said:
And I struggle to see how Intel plans to double core counts at any reasonable TDP.

Oh, Intel simply isn't limited by things like "reasonable TDP". They dream big.

511 · Jan 31, 2025

Geddagod said:
Ah I'm dumb, HB being hybrid bonding makes sense lol.
Yea, I agree, one 8x16 die will prob would be ~100mm2. ARL's die is around the same size IIRC.

It can be a lot smaller if they move the ring bus and L3 to the base die like Clearwater Forest but will not get my hopes up also it's not dumb.
If you wanna see dumb see Intel's Board

https://www.reddit.com/r/intel/s/pG6GKzgz4j

the finances dudes are alright sometimes. they were on top with Otellini. He gets blamed for not entering the smartphone market but, whoops, he actually did try to enter it and build a foundry service but efforts were demolished by Intel's board due to lower margins. Efforts towards a GPU were killed in the same way and demoted to Xeon Phi.

All these years later and again the board cripples a foundry initiative before it even gets off the ground while scapegoating the CEO.

igor_kavinski · Jan 31, 2025

Geddagod said:
I wonder if NVL's new platform may have some high end DDR6 boards, kinda like ADL supporting both ddr4 and ddr5 depending on the mobo.

Yeah that's why they should release NVL-S on LGA1851 to prevent having to waste money on developing a new DDR5 chipset. Let the existing chipset shoulder that burden.

511 · Jan 31, 2025

igor_kavinski said:
Yeah that's why they should release NVL-S on LGA1851 to prevent having to waste money on developing a new DDR5 chipset. Let the existing chipset shoulder that burden.

It's not going to happen NVL will get a new socket if it gets ddr6/PCI-e Gen 6 it will definitely require new board I doubt ddr6 but not PCI-E gen 6

igor_kavinski · Jan 31, 2025

511 said:
It's not going to happen NVL will get a new socket if it gets ddr6/PCI-e Gen 6 it will definitely require new board I doubt ddr6 but not PCI-E gen 6

Still expecting them to act dumb? I guess that's a safe bet

LightningZ71 · Jan 31, 2025

2X8+16 can easily fit within a reasonable TDP. Single and light load boost can still run wild, they just have to keep a rational limit on all-core boost speeds. With 32 e-cores, if they keep them near the sweet spot on the power/frequency curve, they can still have a massive amount of throughput. In those situations, they don't need to run the P cores at high boost speeds either. Keeping them constrained to near the sweet spot can also keep their power draw reasonable.

Saylick · Jan 31, 2025

Geddagod said:
The rumor is 2x 8+16 dies. Not one large one. Even if Intel was to do that, which is not the rumor, I doubt a 16+32 would be much larger than 200mm2, if that. Which is still large mind you, but no where near so large that yields start becoming a massive issue.

Fwiw, in Lunar Lake which was on N3B, the P cores were roughly 4.5mm2 including L2 and the E cores were roughly 1.7mm2 including L2, if we believe this Reddit post: https://www.reddit.com/r/hardware/s/Yo9vTQnk1k

Scaling this up to 8+16 means 64mm2 of compute area, which probably gets a small 15% reduction going to N2, so somewhere around 40-50mm2 after it’s all said and done. Double this for 2x(8+16) and it’s not that much die.

511 · Jan 31, 2025

One Raichu NVL assumption

Kepler_L2 · Jan 31, 2025

Saylick said:
Fwiw, in Lunar Lake which was on N3B, the P cores were roughly 4.5mm2 including L2 and the E cores were roughly 1.7mm2 including L2, if we believe this Reddit post: https://www.reddit.com/r/hardware/s/Yo9vTQnk1k

Scaling this up to 8+16 means 64mm2 of compute area, which probably gets a small 15% reduction going to N2, so somewhere around 40-50mm2 after it’s all said and done. Double this for 2x(8+16) and it’s not that much die.

That's assuming they don't bloat up the core again.

511 · Jan 31, 2025

Kepler_L2 said:
That's assuming they don't bloat up the core again.

I know E core won't be bloated much but can't say anything about P cores

desrever · Jan 31, 2025

511 said:
I know E core won't be bloated much but can't say anything about P cores

e-core is already getting bloated

511 · Jan 31, 2025

desrever said:
e-core is already getting bloated

How? For the performance it is perfectly fine 1.1mm2 excluding cache is perfectly fine for that level of performance and the clock speed it can reach

desrever · Jan 31, 2025

511 said:
How? For the performance it is perfectly fine 1.1mm2 excluding cache is perfectly fine for that level of performance and the clock speed it can reach

area efficiency is down like 50% gen on gen.

SiliconFly · Jan 31, 2025

Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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