Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

Doug S · Saturday at 4:01 PM

DavidC1 said:
There's nothing easy anymore. NOTHING. It's obvious to anyone not lying to themselves and have played with simple GPU voltage/frequency scaling. At about 0.6V it can barely reach 300MHz.

From that point it scales superlinearly in regards to voltage - 5-10% voltage may double frequency, or 1.05x1.05 x 2 = 2.2x power for 2.2x frequency assuming we ignore static leakage+fixed block power.

V/F curve has a superlinear, linear, and sublinear relation depending on what frequency curve you are at. It's not that simple.

It used to be simple as @Abwx claims back in the 0.35u days when the voltages were in the 2-2.5V range. Not anymore. The transistors in modern CPUs have been stuck not far above threshold voltage for a long, long time.

Isn't that supralinear scaling because saturating current for silicon is about 1V so once you get below that domain things start to get squirrely? CPUs used to not operate at all much below that range, but modern techniques have pushed down that minimum voltage bit by bit over time. It isn't so much that ADDING voltage from 0.6V is supralinear, but the design tradeoffs required for reducing voltage below saturating current range exact a bigger cost in operational frequency.

I remember reading a decade ago or so that Intel was doing research into near threshold operation (IIRC about 0.25V, the minimum where silicon transistors can begin to switch 'on') because that was the most power efficient operation range. There were so many tradeoffs designing for operation at such low voltages that they couldn't also operate at "normal" voltages, so they'd only be suitable for very low power roles. Since you have to choose your process for the whole chip it wouldn't be applicable to higher power designs. But in the age of chiplets, who knows. Maybe you can have a chiplet full of near threshold super-E cores that max out well under 1 GHz but possessing 10x-50x the energy efficiency of a regular E core.

Dunno if anything ever came of that research. They may have canceled it once they were forced to admit to the reality that x86 was never going to compete with ARM for very low power embedded roles.

Hulk · Saturday at 4:09 PM

SiliconFly said:
285K media engine fully supports HEVC (H.265) hardware-accelerated encode/decode and should easily beat the competition. Which encoder are you using? Maybe the one you're using doesn't support/use Intel HEVC media engine. Also, Lunar Lake supports VVC (H.266).

Hardware encode is not even close to CPU encode considering quality at a given bandwidth. I only hardware encode.

Thibsie · Sunday at 7:23 AM

Hulk said:
Hardware encode is not even close to CPU encode considering quality at a given bandwidth. I only hardware encode.

Hardware encoding is way faster, no question.
But software encoding is way more flexible.
In hardware, you don't have much flexibility, it's fixed fuctions built-in hardware.. If it doesn't suit you, you're stuck.

Hulk · Sunday at 11:28 AM

DavidC1 said:
16+8 as in 16 Wolves + 8 Coves? Sounds good to me.

Not what I asked.

Same cores. 16+8 or 8+40?

For me 16+8 is good, 8+40 is better, much better.

511 · Sunday at 11:29 AM

Hulk said:
Not what I asked.

Same cores. 16+8 or 8+40?

For me 16+8 is good, 8+40 is better, much better.

NVL is doing 16+32

AcrosTinus · Sunday at 12:05 PM

511 said:
NVL is doing 16+32

This sounds a bit too utopic.
16P cores and 32e on Intel 18A or N2, that is some die size increase on a much more expensive node.

Furthermore if Intel does not have some kind of caching layer for games, the typical reviewers will negate the workstation performance by simply saying AMD XXXX-x3D is faster and more power efficient without adding the constraint "in gaming".

I am done with mainstream anyways for my next build, after the Intel 5820K which was just a dream machine that left no wishes open, everything else that followed was cut down restrained, bugged or plastered with security issues a la Spectre or Meltdown.

HEDT it is now and into the future due to trying to get more into local LLMs as a hobby, the next build is already in motion.

511 · Sunday at 12:10 PM

AcrosTinus said:
This sounds a bit too utopic.
16P cores and 32e on Intel 18A or N2, that is some die size increase on a much more expensive node.

No they are gonna do join 2 8+16 dies so there won't be a monolithic 16+32 die.
If it's 18A it's not much expensive for Intel and jn the end for us vs N2

AcrosTinus said:
Furthermore if Intel does not have some kind of caching layer for games, the typical reviewers will negate the workstation performance by simply saying AMD XXXX-x3D is faster and more power efficient without adding the constraint "in gaming".

I am done with mainstream anyways for my next build, after the Intel 5820K which was just a dream machine that left no wishes open, everything else that followed was cut down restrained, bugged or plastered with security issues a la Spectre or Meltdown.

HEDT it is now and into the future due to trying to get more into local LLMs as a hobby, the next build is already in motion.

Yeah

SiliconFly · Sunday at 1:33 PM

AcrosTinus said:
This sounds a bit too utopic.
16P cores and 32e on Intel 18A or N2, that is some die size increase on a much more expensive node.

Furthermore if Intel does not have some kind of caching layer for games, the typical reviewers will negate the workstation performance by simply saying AMD XXXX-x3D is faster and more power efficient without adding the constraint "in gaming".

I am done with mainstream anyways for my next build, after the Intel 5820K which was just a dream machine that left no wishes open, everything else that followed was cut down restrained, bugged or plastered with security issues a la Spectre or Meltdown.

HEDT it is now and into the future due to trying to get more into local LLMs as a hobby, the next build is already in motion.

It's 18A-P and N2. And it's 2 8+16 dies stitched together. And each one shouldn't be that different from previous gen 8+16 dies.

Also NVL is expected to introduce LLC in the base tile. Should be 144MB.

igor_kavinski · Sunday at 1:38 PM

SiliconFly said:
And it's 2 8+16 dies stitched together.

Any source for that stitching comment? They may be able to "stitch" for server but for consumer, I think it will be very hard to produce something like that in volume. Most likely it's going to be two separate tiles and there will be a latency penalty for workloads that need both tiles.

SiliconFly · Sunday at 1:45 PM

igor_kavinski said:
Any source for that stitching comment? They may be able to "stitch" for server but for consumer, I think it will be very hard to produce something like that in volume. Most likely it's going to be two separate tiles and there will be a latency penalty for workloads that need both tiles.

Sorry abt the confusion. It is separate tiles. I used stitch for foveros. Need a different word.

Hulk · Sunday at 2:15 PM

Based on how close Skymont has come to Lion Cove coupled with the fact that most software will do better with xPcores and 2 or 3x xE cores, it stands to reason that 8 P's and the remaining die space for E's is the way to go.

You would need an application that needs exactly 9-12 cores and not more or less, for example, if you have 8P + 24E for something with 12P to do better. Outside possibly of some games I don't think that exists.

Furthermore, the E cores not being used for the application that requires exactly 9-12 cores will still be using the E's to off-load housekeeping or other applications that are running, thus increasing the performance of that application running on the 8P's or better chiplet on a 9950X.

8 P's running at high frequencies (kind of inefficiently) and 30 or 40 E's running in the sweet spot of the v/f graph is what I want.

AMD is already kind of doing that with the 9950X by using one higher binned compute chiplet (higher frequency) and one lower binned one (lower frequency). I realize this is an economic decision to save the better binned chiplets for other processors in the stack, but even though the 9950X is the flagship product, AMD realizes that most of the gains of a high clocked chiplet come from the first one being loaded.

All of these decisions are driven by economics coupled with real world performance metrics. It's called optimization.

People here constantly want "pie in the sky" products that defy real world economic decision and optimization.

Both AMD and Intel have "told" us the future is a high performance number of cores and a number of lower performing more area efficient and power efficient ones.

Whether it's P's and E's or C's and c's it's the same philosophy.

SiliconFly · Sunday at 2:26 PM

Hulk said:
Based on how close Skymont has come to Lion Cove coupled with the fact that most software will do better with xPcores and 2 or 3x xE cores, there 8 P's and the remaining die space for E's is the way to go.

You would need an application that needs exactly 9-12 cores and not more or less, for example, if you have 8P + 24E for something with 12P to do better. Outside possibly of some games I don't think that exists.

Furthermore, the E cores not being used for the application that requires exactly 9-12 cores will still be using the E's to off-load housekeeping or other applications that are running, thus increasing the performance of that application running on the 8P's or better chiplet on a 9950X.

8 P's running at high frequencies (kind of inefficiently) and 30 or 40 E's running in the sweet spot of the v/f graph is what I want.

AMD is already kind of doing that with the 9950X by using one higher binned compute chiplet (higher frequency) and one lower binned one (lower frequency). I realize this is an economic decision to save the better binned chiplets for other processors in the stack, but even though the 9950X is the flagship product, AMD realizes that most of the gains of a high clocked chiplet come from the first one being loaded.

All of these decisions are driven by economics coupled with real world performance metrics. It's called optimization.

People here constantly want "pie in the sky" products that defy real world economic decision and optimization.

Both AMD and Intel have "told" us the future is a high performance number of cores and a number of lower performing more area efficient and power efficient ones.

Whether it's P's and E's or C's and c's it's the same philosophy.

Then there's LPE cores. Maybe they should come up with HPP cores. Higher Performance P cores.

Dave3000 · Sunday at 6:27 PM

Abwx said:
At this site they know, with Windows updates comparisons for both CPUs.

Test du Ryzen 7 9800X3D : le nouveau maître du jeu !

Loin d'être le succès espéré, les Ryzen 9000 retrouvent de l'intérêt via une baisse de prix et les contreperformances ludiques des Core Ultra 200S. Le moment idéal pour enfoncer le clou avec une version à base de 3D V-Cache, débarrassée des contraintes thermiques limitant ses prédécesseurs.

hardwareand.co

I noticed in that review the X-Plane 12 chart it is showing that the 285k has slightly better 1% lows than the 9800X3D but the 9800X3D has a much higher average. Would this be due to single core IPC/clock speed is more important than a huge L3 cache in that scenario in X-Plane 12 when it hits those 1% lows? Also, does a CPU intensive 3rd party aircraft in X-Plane 12 benefit more from high single-core performance than a large L3 cache if there is a big difference in single-core performance between two CPU's?

Hulk · Sunday at 7:04 PM

Dave3000 said:
I noticed in that review the X-Plane 12 chart it is showing that the 285k has slightly better 1% lows than the 9800X3D but the 9800X3D has a much higher average. Would this be due to single core IPC/clock speed is more important than a huge L3 cache in that scenario in X-Plane 12 when it hits those 1% lows? Also, does a CPU intensive 3rd party aircraft in X-Plane 12 benefit more from high single-core performance than a large L3 cache if there is a big difference in single-core performance between two CPU's?

When the information has to come from main memory then it comes down to which processor has the faster main memory and compute.

OneEng2 · Sunday at 8:36 PM

Panther Lake sounds great .... at least on paper.

I do wonder about the workload in a laptop computer though. For MOST consumers, 8P along with 10 or so E cores would work just fine.

For professionals doing workstation stuff, forget the power and die size and go full in with something crazy like Threadripper.

Still, my biggest concern for Panther Lake isn't performance .... or power ..... but rather profitability. Intel keeps making the foundry out to be the big bad boogie monster and filing all their loss in that one area of the company ..... like it would have been possible to build any of the CPU's of the past at Intel without the foundry!

I think they are still shuffling around the shells in the financial bucket in inventive ways. They scream to the hills that TSMC is too expensive ..... and say how much BETTER profit will be when they get their chips back on 18A internally ..... but HOW? If the foundry is losing all that money, what it means TO ME is that the design area isn't being properly charged for the services they get from the Internal foundry.

I hate company politics though. My life was so much more simple when all I had to do was be an outstanding engineer .

511 · Sunday at 10:18 PM

They have Tax Credit on investment in Fabs and by their own Admissions a I3 wafer is more profitable than I7 wafer for foundry so all they need is to increase the volume of I3/18A wafers significantly to reach any profitability.

The foundry drives their overall GM they say break even by 2027, if they achieve this will be a big thing.

igor_kavinski · Monday at 1:18 AM

Dave3000 said:
Would this be due to single core IPC/clock speed is more important than a huge L3 cache in that scenario in X-Plane 12 when it hits those 1% lows?

Better wait for 9950X3D results before deciding.

DavidC1 · Monday at 4:16 PM

Hulk said:
Not what I asked.

Same cores. 16+8 or 8+40?

For me 16+8 is good, 8+40 is better, much better.

The P core in Nova Lake must be a nice improvement to justify being called a "P core" against Arctic Wolf, or there's something missing where the differences are much closer than even today.

Imagine a CPU where it consisted of a Prescott "P" core and Yonah "E" core.

That's what I meant by 16+8 with 16 being Arctic Wolf. Arrowlake shows that the differences are already so small that 8P is slower than 1P+16E in gaming where it should amplify the differences.

Skymont being so close to Lion Cove is because the P core team is so badly sucking relative to the E. If they were more equal it should be similar to how Gracemont and Golden Cove was. At least the core size differences were justified from the performance difference.

@OneEng2 Don't you mean Novalake, since Pantherlake is mobile only?

Hulk · Monday at 4:47 PM

DavidC1 said:
The P core in Nova Lake must be a nice improvement to justify being called a "P core" against Arctic Wolf, or there's something missing where the differences are much closer than even today.

Imagine a CPU where it consisted of a Prescott "P" core and Yonah "E" core.

That's what I meant by 16+8 with 16 being Arctic Wolf. Arrowlake shows that the differences are already so small that 8P is slower than 1P+16E in gaming where it should amplify the differences.

Skymont being so close to Lion Cove is because the P core team is so badly sucking relative to the E. If they were more equal it should be similar to how Gracemont and Golden Cove was. At least the core size differences were justified from the performance difference.

@OneEng2 Don't you mean Novalake, since Pantherlake is mobile only?

I realize that your knowledge is a lot deeper than mine here. Just want to let you know I appreciate your very informative posts and am only challenging to learn and further discussion.

But as a novice enthusiast in the "CPU Wars" it seems like there would be a lot more low hanging fruit for the monts as they are newer and just a few generations ago had very poor performance relative to the P cores. I mean before Gracemont, we're really talking about very low performing Atom cores, right?

In addition, the P core has been the focus of Intel's drive to create the most performant core possible for almost 50 years.

This gets to the point I've never really understood. It seems like there is only so much instruction level parallelism that can be extracted from the code? Like walking to a wall and decreasing your distance to the wall by half each time you move. Yes, you are continually "getting there" but at a certain point you're really not making headway.

I understand with SMT you can keep increasing "single core" performance as structures get wider, but for ST I just don't see how much improvement can be had with current code?

DavidC1 · Monday at 4:58 PM

Hulk said:
I realize that your knowledge is a lot deeper than mine here. Just want to let you know I appreciate your very informative posts and am only challenging to learn and further discussion.

But as a novice enthusiast in the "CPU Wars" it seems like there would be a lot more low hanging fruit for the monts as they are newer and just a few generations ago had very poor performance relative to the P cores. I mean before Gracemont, we're really talking about very low performing Atom cores, right?

It's simply a human factor, nothing else. Remember the Core uarch revival? Well, they basically got gutted during Kraznich days. Mooly Eden, Dadi Perlmutter all left or got kicked out. And we don't know how many lower level guys left either.

But I have a feeling even those much praised guys weren't the best either. So I'm saying the P core team got even worse.

You read about things on reddit and it's shocking. Like one said Microsoft made a CPU team that was mostly based on former Intel engineers. So much so that the code names they used were identical to the one they used back at Intel. Like the whole division left. Or how Exist keeps saying the entirety of Sapphire Rapids validation team got canned. Who cares about tech when there's no-one developing them?

I think Atom's saving grace during Kraznich days were that they were pushed to be efficient in both power and cost as possible. So they were forced to innovate, or die. While rest of the company were involved in petty politics that plagued the company for decades.

Hulk said:
This gets to the point I've never really understood. It seems like there is only so much instruction level parallelism that can be extracted from the code? Like walking to a wall and decreasing your distance to the wall by half each time you move. Yes, you are continually "getting there" but at a certain point you're really not making headway.

Yes, but things can always be done better. And we know the floor is higher, much higher as demonstrated by the ARM camp.

You say there's a limit right? Well some thought the original Athlon was a marvel and not much more could be done. If you look at the development of Moore's Law, it was around 0.5um days when they thought the end was nigh. Few years ago they pointed out how the pads used in modern processors were bigger than the transistors themselves.

It's clear from the DeepSeek vs OpenAI news that innovation is what keeps things going and it comes from none other than a single source - people working on it. It allows you to beat conventional beliefs and entrenched paradigms. It allows you to "circumvent" laws like the inverse square law.

Even the internal combustion engine is still getting better and better, when you think it's just simple burning fuel source. Always room to fine tune things it seems.

Patent trolls, buying skeletal companies, lawsuits over new inventions, it's all silly nonsense. It's all about people. The AI folks are deluded into thinking that they'll replace the brain and even surpass it one day(peak delusion by guys like Ray Kurzweil), when they don't even understand 1% of 1% how our brain really works.

DavidC1 · Monday at 5:14 PM

Hulk said:
But as a novice enthusiast in the "CPU Wars" it seems like there would be a lot more low hanging fruit for the monts as they are newer and just a few generations ago had very poor performance relative to the P cores. I mean before Gracemont, we're really talking about very low performing Atom cores, right?

It wasn't difficult to see they were playing at a different level ever since Goldmont. You could see from the performance improvement relative to die area and power increase. At the same process the Goldmont Plus offered 30% improvement per clock, clocked 10% higher, while consuming the same amount of power.

And you could see from the architectural innovations that they were far more capable than the P core team, that they were willing to take risks on new ideas, but capable enough to execute on them to make it work.

Simply go and compare new uarch features of both lines. For Core the big thing was Pentium M, Core 2, and Sandy Bridge. Everything from then and between them were very minor and/or just expansions. What new things in Haswell, Skylake, Sunny/Golden/Lion Cove? That's a span of 22 years.

Goldmont brought new ideas, so did Tremont, Gracemont, and Skymont. Things like the clustered decode addresses long-standing x86 bottleneck, the decoders, even more significant than PM, C2, and SNB changes.

Hulk said:
This gets to the point I've never really understood. It seems like there is only so much instruction level parallelism that can be extracted from the code? Like walking to a wall and decreasing your distance to the wall by half each time you move. Yes, you are continually "getting there" but at a certain point you're really not making headway.

Yet the wider processors are faster than the narrower ones. Engineers at Google has said that it can be wider and Jim Keller said this too. Keller made a comment about processors with "Kilo-size ROBs". You tweak things here, and you tweak things there, it all adds up. Bunch of 0.5% improvements add up to cumulative 10, 20, or even 30%.

OneEng2 · Monday at 5:24 PM

DavidC1 said:
@OneEng2 Don't you mean Novalake, since Pantherlake is mobile only?

Well, I meant mobile as Nova Lake is for desktop correct? I was thinking that MOST laptop applications don't require heavy MT performance and are more influenced by battery life and ST performance. Applications that need lots of power are more likely candidates for high end desktop or even workstation setups IMO.

Hulk said:
I understand with SMT you can keep increasing "single core" performance as structures get wider, but for ST I just don't see how much improvement can be had with current code?

I think you get diminishing returns as you double the SMT. AMD currently enjoys a 1.4 uplift using SMT 2 way .... which is really great value for the added transistors needed (~10% as I understand it). Moving to 4 way would require a great deal more execution units and scheduling .... and I think you don't get nearly as good of scaling (someone correct me if I am off base here). I don't think it is so much code dependent as it is how many threads are running since SMT is done in hardware and scheduled by the OS.

DavidC1 said:
I think Atom's saving grace during Kraznich days were that they were pushed to be efficient in both power and cost as possible. So they were forced to innovate, or die. While rest of the company were involved in petty politics that plagued the company for decades.

One could argue that this is the path that a good strategist would take in the current environment where die shrinks are becoming further and further apart ..... and you get less and less from each one. Seems like Intel still believes that they can fund this insanity forever when in fact, this will all come down to efficiency as you mentioned. It isn't just about who can make the fastest processor, it is about who can make the fastest processor and make money doing it!

DavidC1 · Monday at 6:09 PM

OneEng2 said:
Seems like Intel still believes that they can fund this insanity forever when in fact, this will all come down to efficiency as you mentioned. It isn't just about who can make the fastest processor, it is about who can make the fastest processor and make money doing it!

They are suffering financially in a market with uptrend. If they do not reverse this quick, when the downtrend happens, they will be gone.

511 · 2025-02-04T07:19:51-0500

DMR Launching Q2/Q3 26?

511 · 2025-02-04T08:06:57-0500

DavidC1 said:
They are suffering financially in a market with uptrend. If they do not reverse this quick, when the downtrend happens, they will be gone.

Well I don't think so cause they have not benefited from AI as much other companies

Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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