Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

DisEnchantment · Apr 24, 2020

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.

N7 performance is more or less understood.

This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

511 · Feb 6, 2025

jpiniero said:
But they don't have enough next gen capacity for their own products. It looks like they are going to have to use TSMC for a large part of their products for the forseeable future because they simply don't have enough.

What even after ramping 2 Fabs at Arizona and at Ireland they don't have enough capacity i doubt it?

jpiniero said:
Not to mention selling Raptor Lake until they can't.

Yes

dttprofessor · Feb 6, 2025

Intel have definitly ordered N2 by Pat for backup，just for backup.

Thibsie · Feb 6, 2025

dttprofessor said:
Intel have definitly ordered N2 by Pat for backup，just for backup.

Sure

OneEng2 · Feb 6, 2025

cannedlake240 said:
Powervia imposed thermal limitations, which N2/P isn't affected by, making it not suitable for desktop CPUs? Curious what happens with A16...

I know that BSPDN in general has caused issues with hot spots in the die that limit the overall clock speed attainable. The speculation by some is that perhaps Intel has found a way to get around it.

Me, I think that it is likely that there are risks to BSPDN that make it a gamble ..... especially when you are moving to GAA in the same node. For some time I have stated I think that Intel is throwing a "hail Marry" pass. High risk, high reward.

I am very worried for 18A at Intel. There are serious risks involved with so many changes in a single step. Furthermore, the design CAN'T be easily moved to a lower risk node at Intel.

TSMC on the other hand is doing GAA design on N2 first, then using a library-compatible process on A16 to de-risk designs that attempt to use GAA and BSPDN.

Intel's plan? Do both GAA and BSPDN in one step, then move the entire process to High NA machines for the next step. It's stupid IMHO. So much risk packed into so few steps costing SO much money.

If Intel pulls this off, it will be the biggest inside straight in modern corporate history IMO.

DKR · Feb 6, 2025

OneEng2 said:
I am very worried for 18A at Intel. There are serious risks involved with so many changes in a single step. Furthermore, the design CAN'T be easily moved to a lower risk node at Intel.

Intel management said 18A is doing well (many times now- Pat, Dave, Naga & Michelle), so nothing to worry just yet!. Also Dr. Ian Cutress had this to say about the Intel 18A health.

Intel 2024 Q4 Financials

Outlook is Looking Better after Q3

morethanmoore.substack.com

About the thermals of BSPDN/ PowerVia, Intel derisked this BPSDN technology with an internal node based Intel 4 test chip called Blue Sky Creek that was made on a Intel 4 + BPSDN. and had this to say about it

With PowerVia, Intel Achieves a Chipmaking Breakthrough

Intel’s Ben Sell explains how the company developed and proved the world's first backside power solution, taking a major step forward in chipmaking.

www.intel.com

For instance, heat. “Normally you use the silicon side also for heat dissipation,” Sell explains. “So now you have sandwiched your transistors and the question is, ‘Do we have a thermal problem? Do we get a lot of local heating?’” At this point you can probably guess the answer: no.

Some unfortunate stuff at the end though!

As for PowerVia, it has no peer. According to recent reports, Intel’s planned 2024 introduction of PowerVia would put competitors “roughly two years behind” when it comes to backside power.
“At least for this time period,” confirms Sell, “we have a quite competitive backside power delivery option.”
Your first opportunity to feel the many benefits of PowerVia will come next year in the form of Arrow Lake, a next-generation Intel processor for PCs built using the Intel 20A process. Its billions of transistors will be inverted, working more efficiently than ever.

There is more information about this blue sky creek test chip in here (including a yield offset of 2Q for with & without BSPDN).

Intel Details PowerVia Backside Power Delivery Technology

A key feature of Intel's 18A and 20A nodes revealed

www.tomshardware.com

OneEng2 · Feb 6, 2025

DKR said:
Intel management said 18A is doing well (many times now- Pat, Dave, Naga & Michelle), so nothing to worry just yet!. Also Dr. Ian Cutress had this to say about the Intel 18A health.

Intel 2024 Q4 Financials

Outlook is Looking Better after Q3

morethanmoore.substack.com

View attachment 116476

About the thermals of BSPDN/ PowerVia, Intel derisked this BPSDN technology with an internal node based Intel 4 test chip called Blue Sky Creek that was made on a Intel 4 + BPSDN. and had this to say about it

With PowerVia, Intel Achieves a Chipmaking Breakthrough

Intel’s Ben Sell explains how the company developed and proved the world's first backside power solution, taking a major step forward in chipmaking.

www.intel.com

Some unfortunate stuff at the end though!

There is more information about this blue sky creek test chip in here (including a yield offset of 2Q for with & without BSPDN).

Intel Details PowerVia Backside Power Delivery Technology

A key feature of Intel's 18A and 20A nodes revealed

www.tomshardware.com

I hear you. You certainly aren't the only one that is in this camp "everything seems OK".

I would like to point out, that that 20A they were talking about .... was canceled. The entire roadmap for 2025 was just delayed. The first chip they will make using 18A is no longer the large die CWF, but rather the smaller tiles in Panther Lake. Both designs need not clock as high as desktop or workstation, and both will likely be power limited vs thermally limited.

That isn't the case in higher performance cores.

I guess lots of my worry stems from a history of Intel "swing-and-a-miss".... and lots of those misses involved a good deal less risk than they are taking on 18A IMO.

Lets hope I am wrong. A good 18A for Intel is good for all of us.

cannedlake240 · Feb 7, 2025

OneEng2 said:
I know that BSPDN in general has caused issues with hot spots in the die that limit the overall clock speed attainable. The speculation by some is that perhaps Intel has found a way to get around it.

Me, I think that it is likely that there are risks to BSPDN that make it a gamble ..... especially when you are moving to GAA in the same node. For some time I have stated I think that Intel is throwing a "hail Marry" pass. High risk, high reward.

I am very worried for 18A at Intel. There are serious risks involved with so many changes in a single step. Furthermore, the design CAN'T be easily moved to a lower risk node at Intel.

TSMC on the other hand is doing GAA design on N2 first, then using a library-compatible process on A16 to de-risk designs that attempt to use GAA and BSPDN.

Intel's plan? Do both GAA and BSPDN in one step, then move the entire process to High NA machines for the next step. It's stupid IMHO. So much risk packed into so few steps costing SO much money.

If Intel pulls this off, it will be the biggest inside straight in modern corporate history IMO.

The new product CEO pretty much confirmed that 18A is below N2. The question is by how much, single digit or a 15%+ full node gap...

DKR · Feb 7, 2025

OneEng2 said:
I would like to point out, that that 20A they were talking about .... was canceled. The entire roadmap for 2025 was just delayed. The first chip they will make using 18A is no longer the large die CWF, but rather the smaller tiles in Panther Lake. Both designs need not clock as high as desktop or workstation, and both will likely be power limited vs thermally limited.

MJH said CWF moved to 2026 due to complicated packaging requirements - exact quote below from Q4'24 earnings call (didn't even say any issue but could be the case). So they are working out issues with Foveros 3D which I think uses hybrid bonding. Intel also delayed half the hybrid bonding machines delivery from BE Semiconductor Industries last quarter. So that points out packaging is the issue.

And 18A is doing just fine on a performance and yield for Granite Rapids, but it does have some complicated packaging expectations that move it to 2026. But we expect that to be a good product and continue to close the gap as well.

Also CWF is not a large die product. It has 12 x 18A compute die chiplets placed on top of a large Intel 3-T interposer. For total 288 cores (top end CWF SKU), that comes out as 24 E cores on each compute die. We know 4 E core cluster is slightly larger than 1 P core in Arrow Lake (I don't know the exact dimensions). Assuming each E core is 0.33 P core size, 24 E core would be equivalent to 8 P cores. So the compute tiles on the CWF is not really that big compared to typical desktop compute tile. Probably same size as PTL SKU tile. Also the Intel 3-T interposer supposed to have the L3 cache (I am not 100% sure if it is L3 or LLC). You don't see the chiplets in real world picture below because the compute tile is underneath the cache tile (flipped).

To me everything points to the packaging and not Intel 18A 🤞 like they said. But even that is not ideal. Didn't Intel boast they have leadership in advanced packaging?

OneEng2 · Feb 7, 2025

DKR said:
MJH said CWF moved to 2026 due to complicated packaging requirements - exact quote below from Q4'24 earnings call (didn't even say any issue but could be the case). So they are working out issues with Foveros 3D which I think uses hybrid bonding. Intel also delayed half the hybrid bonding machines delivery from BE Semiconductor Industries last quarter. So that points out packaging is the issue.

Also CWF is not a large die product. It has 12 x 18A compute die chiplets placed on top of a large Intel 3-T interposer. For total 288 cores (top end CWF SKU), that comes out as 24 E cores on each compute die. We know 4 E core cluster is slightly larger than 1 P core in Arrow Lake (I don't know the exact dimensions). Assuming each E core is 0.33 P core size, 24 E core would be equivalent to 8 P cores. So the compute tiles on the CWF is not really that big compared to typical desktop compute tile. Probably same size as PTL SKU tile. Also the Intel 3-T interposer supposed to have the L3 cache (I am not 100% sure if it is L3 or LLC). You don't see the chiplets in real world picture below because the compute tile is underneath the cache tile (flipped).

To me everything points to the packaging and not Intel 18A 🤞 like they said. But even that is not ideal. Didn't Intel boast they have leadership in advanced packaging?

View attachment 116503 View attachment 116504

I have heard quite a lot of claims by Intel recently that didn't turn out to be true. I no longer consider Intel's statements in timing to be supportive of real-world timing, but rather more their hopes and dreams for the timing.

Perhaps it is just the packaging, and 18A is doing very well? I doubt we will ever know.

cannedlake240 · Feb 7, 2025

OneEng2 said:
I have heard quite a lot of claims by Intel recently that didn't turn out to be true. I no longer consider Intel's statements in timing to be supportive of real-world timing, but rather more their hopes and dreams for the timing.

Perhaps it is just the packaging, and 18A is doing very well? I doubt we will ever know.

How can Clearwater that has 55mm2 18A tiles be delayed >2q due to process issues while panther thats over 114mm2 with a lot more ip stays on track? The main difference between the two is advanced packaging. Clearwater uses hybrid bonding + active interposer and has 17 tiles in total. PTL is the usual passive base and 3 main tiles

maddie · Feb 7, 2025

DKR said:
Didn't Intel boast they have leadership in advanced packaging?

Didn't Intel boast at various times that they were leaders in pretty much everything?

cannedlake240 · Feb 7, 2025

Prediction for IFS node perf/w:
18A is N4P +-5%, N3 series advantage will be most pronounced at low voltage
18AP is then somewhere in N3B to N3P range
14A(official number +15% over 18A) ≈ N3P to N2 range

Won't rule out even lower numbers but It seems unlikely. Would be curious If 14A somehow regained some of the lost ground on 18A regression

DavidC1 · Feb 7, 2025

cannedlake240 said:
Prediction for IFS node perf/w:
18A is N4P +-5%, N3 series advantage will be most pronounced at low voltage
18AP is then somewhere in N3B to N3P range
14A(official number +15% over 18A) ≈ N3P to N2 range

Typically, Intel had a performance lead while being half a gen behind in density and factors fitting low power parts such as performance at low power and leakage.

18A-P being N3B level performance would be a disaster and be actually behind Intel 3. Then the regular 18A would be behind Intel 4.

cannedlake240 · Feb 7, 2025

DavidC1 said:
Typically, Intel had a performance lead while being half a gen behind in density and factors fitting low power parts such as performance at low power and leakage.

18A-P being N3B level performance would be a disaster and be actually behind Intel 3. Then the regular 18A would be behind Intel 4.

Not perf, performance per watt. Tsmc nodes are far ahead of intel at low voltage perf

DKR · Feb 7, 2025

cannedlake240 said:
18A is N4P +-5%, N3 series advantage will be most pronounced at low voltage

This is a very pessimistic take. Even TSMC was saying 18A is equivalent to N3P. Or if you are charitable to Intel, you can say that C.C. Wei is slightly underselling his competitor and come to a conclusion that Intel 18A is superior to N3P. That would put Intel 18A on par with TSMC's offerings in 2025. Only question is can Intel deliver that in volume and with good yield.

Actually, we do not underestimate any of our competitors or take them lightly. Having said that, our internal assessment shows that our N3P -- now, I'll repeat again, N3P technology, demonstrated comparable PPA to 18A, my competitors' technology, but with an earlier time to market, better technology maturity, and much better cost. - C.C. Wei, CEO, TSMC.

TSMC Places Confidence In 3nm Node, Compares It To Intel 18A: Better Maturity, Cost & Delivery Time

TSMC believes that it will retain its process leadership over Intel's 18A node with its 3nm process owing to better maturity & cost.

wccftech.com

maddie said:
Didn't Intel boast at various times that they were leaders in pretty much everything?

Well, they were leaders at most things before falling from grace.

cannedlake240 · Feb 7, 2025

DKR said:
This is a very pessimistic take. Even TSMC was saying 18A is equivalent to N3P. Or if you are charitable to Intel, you can say that C.C. Wei is slightly underselling his competitor and come to a conclusion that Intel 18A is superior to N3P. That would put Intel 18A on par with TSMC's offerings in 2025. Only question is can Intel deliver that in volume and with good yield.

TSMC Places Confidence In 3nm Node, Compares It To Intel 18A: Better Maturity, Cost & Delivery Time

TSMC believes that it will retain its process leadership over Intel's 18A node with its 3nm process owing to better maturity & cost.

wccftech.com

Well, they were leaders at most things before falling from grace.

Just trying to be realistic. I doubt tsmcs statement still holds true after i18A regressed, likely due to 20A having issues, since they share the same base. Hopefully they can regain some or all the perf in 14A, that'd mark the beginning of true competition at the leading edge.

Meteor Late · Feb 7, 2025

Well I've been saying N3P all this time, now it's time to downgrade 18A to N3E in terms of performance per watt.
My reasoning is very simple, 20A cancelled + how would a company that has been a disaster after disaster in terms of process nodes suddenly surpass TSMC out of nowhere? Intel suddenly got good and is better than TSMC at nodes? with Intel's disastrous culture?
What's more likely here is that 20A was a major disaster and that's why it was cancelled, and now the improvements and fixes they made will mean they can launch what 20A should've been, but renamed to 18A, this is my expectation.

cannedlake240 · Feb 7, 2025

Maybe they chose to outsource top end NVL as a hedge when it was clear 20A was doing poorly and 18A was uncertain, or for capacity reasons. However all this sounds like cope, when there is a much simpler explanation from the CEO "we chose the node that allows us to win"

Saylick · Feb 7, 2025

I'm firmly in the camp that Intel 18A is a N3P competitor in PPA, and may win out in perf/W but at a lower density. Of course, it would be advantageous for Intel to use an internal node for cost reasons but they have a comparatively small number of EUV machines and are thus capacity limited to move everything in-house. They therefore need to pick and choose where to use Intel 18A. From an optics standpoint, it would be wise for Intel to use 18A on products or SKUs which can favorably showcase the best aspects of the node because the whole industry will be scrutinizing it's first commercial use. Getting external customers to use 18A will be a battle still, since there's not a lot of capacity and it's a risky bet to move away from TSMC.

OneEng2 · Feb 7, 2025

cannedlake240 said:
How can Clearwater that has 55mm2 18A tiles be delayed >2q due to process issues while panther thats over 114mm2 with a lot more ip stays on track? The main difference between the two is advanced packaging. Clearwater uses hybrid bonding + active interposer and has 17 tiles in total. PTL is the usual passive base and 3 main tiles

Not saying you are wrong here, but where did you get the 55mm2? It does wash on casual inspection though since current N3B Skymont is ~ 1.73mm2 with cache. Darkmont is likely to have more complexity and more cache.

Makes sense.

Saylick said:
I'm firmly in the camp that Intel 18A is a N3P competitor in PPA, and may win out in perf/W but at a lower density. Of course, it would be advantageous for Intel to use an internal node for cost reasons but they have a comparatively small number of EUV machines and are thus capacity limited to move everything in-house. They therefore need to pick and choose where to use Intel 18A. From an optics standpoint, it would be wise for Intel to use 18A on products or SKUs which can favorably showcase the best aspects of the node because the whole industry will be scrutinizing it's first commercial use. Getting external customers to use 18A will be a battle still, since there's not a lot of capacity and it's a risky bet to move away from TSMC.

I would tend to agree with this. I also think that N2 is going to be a bit of a let down as well though. We will see.

jdubs03 · Feb 7, 2025

cannedlake240 said:
Maybe they chose to outsource top end NVL as a hedge when it was clear 20A was doing poorly and 18A was uncertain, or for capacity reasons. However all this sounds like cope, when there is a much simpler explanation from the CEO "we chose the node that allows us to win"

Nothing has been reported so far about which process node Nova Lake will use. We know Intel was the first customer of ASML to use high-NA equipment. It stands to then reason then that they’ll then be further along with getting products out in which this equipment was used. So I wouldn’t be so sure that Nova Lake will use TSMC N2.

cannedlake240 · Feb 8, 2025

OneEng2 said:
It does wash on casual inspection though since current N3B Skymont is ~ 1.73mm2 with cache. Darkmont is likely to have more complexity and more cache

Darkmont is a minor 'tick' uarch, same as Crestmont. Intel also released wafer pics with chips that look suspiciously similar to what CWF tiles with 6 Atom clusters would look like, with tiles sizes roughly matching the rumored number. There's been no indication of changes to L2 cache, but L3 is confirmed to be in the base tile and more than doubled capacity.

jdubs03 said:
We know Intel was the first customer of ASML to use high-NA equipment.

14A enters production in 2027 1H best case. Following traditional 2 year cadence of process technology. NVL launch is q4 26 so the N2 rumor seems pretty accurate

cannedlake240 · Feb 8, 2025

Saylick said:
I'm firmly in the camp that Intel 18A is a N3P competitor in PPA, and may win out in perf/W but at a lower density.

This i'd still consider a decent win, even with the cost considerations. It's not like tsmc can keep using finfets, they too will soon be using GAA and Super power rail. That'd mean 14A has a slim chance to be a legit contender for the top spot.
By 2h of 2026 they should have 1 decent sized fab fully ramped (>20k wspm). I guess with PTL being the first high volume product since Raptor +DMR, CWF, WCL and some foundry customers sprinkled in capacity might be a concern, it's hard to tell. Again, could be a hedge too in case 18A failed, most of the NVL lineup launches on time since it's such an important gen for mkt share

biostud · Feb 8, 2025

LightningZ71 said:
People really don't appreciate the bind that the West is in regarding computer supply chains. In a situation where things go sideways in Southeast Asia, the large regional power can easily interdict every supply chain that feeds the West either whole product or critical components for the rest of their products. It's not just processors either; all up and down the list of parts are ingredients that come from that area. Even for products advertised as being all Intel internally sourced tiles are process steps or subcomponents that come from overseas. AMD is essentially without product.

Yeah, but ASML sells the equipment to TSMC, so they also depends on equipment from "the West". It's all connected.

Gideon · Feb 10, 2025

More info on TSMC 2nm:

https://www.reddit.com/r/hardware/s/lW3rXU4NOq

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