Has anyone done CCD<->CCD latency tests yet?
I'm very interested if the new interconnect improves that.
Bit worse than Granite Ridge (after the bug fix).
D2D latency is honestly pretty meaningless as far as metrics go. For all the cope over 180ms of D2D latency, the "fix" changed very little in terms of performance.Bit worse than Granite Ridge (after the bug fix).
I heard the fix was only to make sure latency was measured correctly in the artificial workload used to measure it...D2D latency is honestly pretty meaningless as far as metrics go. For all the cope over 180ms of D2D latency, the "fix" changed very little in terms of performance.
is Strix Halo's CCD different from Turin's CCD too?
Yes, they have different interfaces active. The AMD of the past would have them both present in the same physical design, one active, one fused off. The AMD of the present though? This is why I asked.different d2d interface.
Or simply cut off, a 0.05mm reserved width is way enough for the purpose, anyway it s doubtfull that they used a different die for such a small difference.Yes, they have different interfaces active. The AMD of the past would have them both present in the same physical design, one active, one fused off.
Yes, they have different interfaces active. The AMD of the past would have them both present in the same physical design, one active, one fused off. The AMD of the present though? This is why I asked.
(My other question concerning the artistic renderings was partially directed to the other poster who I cited.)
((As it turns out, the AMD of the present is doing this differently than the AMD of the past. This alone is not surprising at all, of course. But that they did it with a presumed low~ish volume part is something which is not intuitive for me at least.))
True, but imagine this scenario:
- Strix Halo interface is identical to Zen 6
- AMD develops new desktop (AM5) IOD also compatible with this interface in 2025
- AMD switches desktops to the new IOD, Strix Halo CCD
- in 2026, when Zen 6 CCD is ready, AMD just switches CCDs
In other words, a phased approach. One side benefit: AMD can bin CCDs between Strix Halo and desktop.
What would prompt AMD to release a new IOD for desktop early? Dell. Dell wants NPU on every new PC in the near future.
Then it's HP and Lenovo they want to please.If I was AMD I wouldn't a crap about what Dell wants for what should be obvious reasons.
Then it's HP and Lenovo they want to please.
If I was AMD I wouldn't a crap about what Dell wants for what should be obvious reasons.
I don't think they will use this exact CCD elsewhere.Doing a different mask for a highly similar CCD for a product that will sell in extremely paultry numbers is financial suicide... If you don't have a solid plan to use those EXACT CCDs elsewhere.
This is just speculation on my part, but it seems to me that Dell is furious at Intel. For not being competitive, for rising prices, for less discounts / incentives / bribes, for Raptor Lake degrading CPU fiasco.
This is just speculation on my part, but it seems to me that Dell is furious at Intel. For not being competitive, for rising prices, for less discounts / incentives / bribes, for Raptor Lake degrading CPU fiasco.
And how furious do you think AMD is at Dell? If I was AMD HP would get first dibs, Dell last. Of course I know nothing of the market conditions these days.
If you slow down7ish hours until this, I hope slides get released online soonish.
If you slow down(they provide the timestamps) Zen 5 related part, you are able to read all the slides. Since I was unable to listen in at the time, I haven't listened to their comments.
Funny thing AMD downgraded Zen4 FPU to be 3 wide for the purposes of this comparison, since this is mentioned twice on different slides, I doubt it's just a type. So either someone did not read the Zen4 software optimization manual, or that manual was not telling the full story.
Here is generational per-computer performance (that is, neither clock- nor core-count- nor power-normalized) as claimed by AMD:Sometimes generations that are supposed to be huge improvements fall flat, and sometimes generations that are rumored to be minor end up being surprisingly good. Zen+ had no architectural changes and it was 13% faster. Zen2 was rumored to be huge (so many people saying "low hanging fruit" and comparing it to sandy bridge), and it was only 18% faster. Then Zen3 was 21% faster. based off TPU's numbers
If you slow down(they provide the timestamps) Zen 5 related part, you are able to read all the slides. Since I was unable to listen in at the time, I haven't listened to their comments.
Funny thing AMD downgraded Zen4 FPU to be 3 wide for the purposes of this comparison, since this is mentioned twice on different slides, I doubt it's just a type. So either someone did not read the Zen4 software optimization manual, or that manual was not telling the full story.
Intel is competitive - at least in 1P. DDR8800 might help a bit.Surprising slide imo.