Discussion AMD SoC Halo series GPU discussion

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fastandfurious6

Senior member
Jun 1, 2024
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Medusa Halo with 48 CUs and 384-bit bus according to MLID. No mention of uarch (hopefully it's 12/12.5/13) and if it's 12-channel LP5 or 8-channel LP6.

the point is, Medusa Halo will 100% play everything on QHD Ultra, even playable 4K with medium settings

LLM perf will be decent for the model sizes it can handle

what else? basically we enter an era where "5090" behemoth-type cards will become obsolete except enthusiasts who want 4K/8K Ultra or whatever
 
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Glo.

Diamond Member
Apr 25, 2015
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That's why Medusa Point is still RDNA 3.5 I suppose? in an even worse memory bandwidth scenario, we make things more difficult for the iGPU? it's the magic juice that AMD won't give to the masses?
The reason is simple why Medusa and further mainstream dies would get R3.5. Transistor budget. RDNA3.5 compared to RDNA4 is much less transistor starved.

ON the other hand.

Since we now consider MLID to be reliable source, and not somebody who can be made fun of by giving him fake leaks, 200 mm2 for the IOD alone is quite... big.

And if MLID's schematics are correct the iOD has 16 CUs. Even accounting for the NPU and even Infinity cache for the iGPU. So where did the transistor budget go on 3 nm process?

Either it is RDNA4, or even UDNA, or the iGPU is MUCH larger than just 16 CUs. If MLID is correct and Medusa Halo has 48 CUs, then logical would be 24 CUs, even with RDNA3.5.
 

Jan Olšan

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Jan 12, 2017
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Medusa Halo with 48 CUs and 384-bit bus according to MLID. No mention of uarch (hopefully it's 12/12.5/13) and if it's 12-channel LP5 or 8-channel LP6.

View attachment 118760
Doesn't 256bit-bus version pretty much mean it must be LPDDR5X? You can't make that width out of 24bit-interface LPDDR6 chips. (Of course, there is always option of MLID being wrong one or multiple out of those claims, or all.)
 

TESKATLIPOKA

Platinum Member
May 1, 2020
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RDNA4 has better power and BW efficiency than RDNA3.5.
For a product like Strix Halo or other APUs, that is pretty crucial.
As I said before, top level CPU but mediocre GPU. With RDNA4 It would be way more usable.
Not like you can't use RDNA3.5, but If AMD at the same time introduces an architecture, which significantly improves on the previous architecture in many areas, you just ask yourself If It's worth it. I must say that Strix Halo is not worth It for me.
 

maddie

Diamond Member
Jul 18, 2010
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The questions is how much more area.
If RDAN3.5 offers better performance per area, then ok, but does It? I don' know.
Try using the transistor numbers as an indicator of size. RDNA 4 has a very large transistor budget for 64 CU.
 

maddie

Diamond Member
Jul 18, 2010
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Transistor count is not that important but transistor density.
Not for your concern, which is the RDNA 3.5 and RDNA 4 area issue. For a given node you will be able to see the transistor (area) saving by using either, at least approximately. Or are you comparing the two on different nodes, which would be crazy.
 

fastandfurious6

Senior member
Jun 1, 2024
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my guess: AMD wanted to ship Halo with RDNA4 (of course) but limitations/constraints are a real thing

maybe they needed another 6-12 months to have that ready, maybe it was given no-go. most probably

chips way too complex for quick prototype iterations
 

leoneazzurro

Golden Member
Jul 26, 2016
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RDNA4 has better PPA than RDNA3 for sure. But in mobile PPW is generally first priority. So you have to balance both.
 
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uzzi38

Platinum Member
Oct 16, 2019
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RDNA4 has better PPA than RDNA3 for sure. But in mobile PPW is generally first priority. So you have to balance both.

I mean, RDNA4 looks significantly improved on that end too. And when you compare Strix Halo to a CPU+dGPU config, Strix Halo kind of doesn't scale up to a high enough power level that makes sense for gaming laptops. Most gaming laptops have the cooling headroom for 80W+ for dGPU alone, Strix Halo starts petering out at 80W for both light CPU use and heavy GPU use at the same time. Being able to scale a little higher wouldn't be a bad thing.
 

poke01

Diamond Member
Mar 8, 2022
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Much better than M2 gen.



$3.5 for $128GB. Framework might want to update those slides since it’s not shipping till Q3 lol.
 

okoroezenwa

Member
Dec 22, 2020
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Almost seems like Apple is caring about wanting to compete now, for a change. Or did they get a really crazy deal on RAM?
Is this better pricing than the M2 gen? It seems the same to me. And Framework/AMD with 2k for 128GB RAM still seems like a good deal.
 

MS_AT

Senior member
Jul 15, 2024
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$3.5 for $128GB.
If it only was 3.5$ I would buy it myself (sorry couldn't help it)

On more serious note, while it offers 2x the bandwith it cost almost twice as much. And 1.5k over my budget.

Thus I am staying with framework until better deal on Halo appers. Especially seeing staying on x64 saves me migration time.
 

poke01

Diamond Member
Mar 8, 2022
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On more serious note, while it offers 2x the bandwith it cost almost twice as much. And 1.5k over my budget.
You also get a better GPU and CPU and faster I/O.

Thus I am staying with framework until better deal on Halo appers. Especially seeing staying on x64 saves me migration time.
Yep, the Framework still has its place and much cheaper.

Now I do hope NV digits is not 256GB/s for 3K cause then all it has going for is CUDA.
 
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TESKATLIPOKA

Platinum Member
May 1, 2020
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Not for your concern, which is the RDNA 3.5 and RDNA 4 area issue. For a given node you will be able to see the transistor (area) saving by using either, at least approximately. Or are you comparing the two on different nodes, which would be crazy.
RDNA3 vs RDNA2 WGP


or
Navi 33(N6): 65.2 MTr/mm2 (100%)
Navi 48(N4C): 151.2 MTr/mm2 (232%)

That's not only thanks to a better node. That was my point.
Simply looking at the increase in transistor count doesn't tell you everything.
 
Last edited:

Joe NYC

Platinum Member
Jun 26, 2021
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TLDR:

In addition to previous video of MLID, where he said Medusa Halo may be 44 CUs and memory bus width may go from 256 to 384 bits, in this video, he says that memory may be LPDDR6.

Is seems that LPDDR6 availability might start late 2025, early 2026, so theoretically, this could be feasible time wise. But after betting on new memory technology (DDR5) and getting burned, AMD may be hesitant to be on the bleeding edge.

IMO, there is a solution: Go to MoP design, and place a fixed price order with one of the memory makers for the memory - which would shield the OEMs from initial price fluctuations.

Considering the shambles Samsung is in, as far as their fabs, Samsung could jump on this.

 

Joe NYC

Platinum Member
Jun 26, 2021
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it's not.

It did not seem super credible, and he did not seem to confident. Just throwing it out there...

that's not viable at -halo volumes. Get real.

We don't know what the volumes will be of the Halo parts. But Apple is doing it, and is going to continue to do it. Intel is doing it, to some extent, but doesn't want to continue to do it.

What do you think Lunar Lake volume is vs. Strix Halo for the rest of 2024, unit wise?

Halo would most likely have on average 2x or more memory than Lunar Lake, which would make it more expensive (up front).
 
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