Question Zen 6 Speculation Thread

OneEng2 · Mar 9, 2025

Markfw said:
I agree that apple has good IPC, but not 50% higher, and its not a competitor of Zen or Intel. And 50% higher clock rates ? 7.5 ghz .. No way.

So wrong on 3 counts.

I generally believe that the line of thinking that ARM is somehow architecturally superior to x86 is flawed ... and has been since x86 went super-scaler and had to have equal length instruction and data to push through the pipes for the design to work.

Now, it is more a matter of what your design goals are. One design may be much more power efficient for mobile (ie, maximize performance within a very low power envelope), but sacrifice max clock speed. Another design might need lots of small cores and lots of bandwidth to move DC loads through.

I strongly believe in the engineering concept of "You don't get something for nothing". Good engineering is then attempting to best make use of strengths and weaknesses of each approach for a given problem or use model.

Certainly, there has been times when Intel dominated the industry, but in those times IIRC, they also had a huge foundry advantage as well. It's much more difficult to "dominate" now when pretty much everyone is stuck with the same fundamental foundry advantages and costs.

Yea, I know Intel keeps touting how they will be more cost effective on 18A; however, I seriously have my doubts about that statement. That equipment is GOD awful expensive. I would like to see an ROI calculated for the 20bn plus expenditure Intel has in 18A already. I suspect if you tried to spread it over the chips it will produce, it may not even look as cost effective as paying TSMC for N2 .... but that is pure, unadulterated speculation .

Kepler_L2 said:
32C CCD is just for servers

I thought that as well. This link: https://wccftech.com/amd-next-gen-ryzen-zen-6-medusa-ridge-cpus-12-24-32-core-up-to-128-mb-l3-cache/

Refers to the 32 core part under "Medusa Ridge" which is AMD's Zen 6 desktop parts as I understand it.

It does kinda make sense. If AMD is already making the 32 core N2 Zen 6c CCD for server, why not combine the same CCD on the desktop with the desktop IOD and provide a 32 core part for desktop?

Intel is reportedly going to have a 52 core Nova Lake (16P, 32E, 4 LPE). Maybe the AMD 32 core, 64 thread desktop part is designed to compete with this monster?

If 1 Zen core = 1.5 Intel E cores The 24 core Zen 6 (two 12c Zen 6) would be equal to 36 E cores, but would still be down 16P cores in MT performance (which for argument's sake I am saying is 1P = 1Zen 6).

The 32 core Zen 6c would have an additional 8 cores to combat the 16P cores. My guess is it still won't keep up with Nova Lake's 52 cores though... thus my speculation on a 64c Zen 6 desktop behemoth to trump Nova Lake with.

Still, most people will not get any benefit at all from all these cores .... and furthermore, for applications that can utilize the cores, it starts getting really hard to feed them with just 2 channels of memory.

OneEng2 · Mar 9, 2025

poke01 said:
So its likely R5 8C/16T, R7 12/24T, R9 24/48T

I think the 10700X might beat the 9950X in MT benchmarks. Could this be the first Ryzen 7 to beat the previous Ryzen 9?

I wouldn't be surprised if things were more granular than that.

AMD isn't likely to make ANY CCD's less than 12c IMO (I could be wrong though). If that is the case, then:

2CCD's that yield perfect gets you 24c.
1CCD that yields perfect gets you 12c.
Some CCD's will yield 10c good on a CCD (they have to work in pairs) That gives you the potential for:
- 2CCD 20c
- 1CCD 10c
Some CCD's will yield 8c good on a CCD. That gives you:
- 2CCD 16c
- 1CCD 8c
A really bad CCD could yield only 6c on a CCD. That gives you:
- 2CCD 12c
- 1CCD 6c

Of course, the 2CCD versions will have double the cache so will perform better in some apps by a lot.

I don't know how AMD plans to slice this marketing mess though. Maybe 8 variants in core count alone is too much? Then imagine 3 frequency bins! Dizzying .

poke01 · Mar 9, 2025

OneEng2 said:
Intel is reportedly going to have a 52 core Nova Lake (16P, 32E, 4 LPE). Maybe the AMD 32 core, 64 thread desktop part is designed to compete with this monster?

It would be interesting to see this from Intel. I do think it will cost $1000+USD and out of reach for many users.

Kepler_L2 · Mar 9, 2025

OneEng2 said:
I thought that as well. This link: https://wccftech.com/amd-next-gen-ryzen-zen-6-medusa-ridge-cpus-12-24-32-core-up-to-128-mb-l3-cache/

Refers to the 32 core part under "Medusa Ridge" which is AMD's Zen 6 desktop parts as I understand it.

It does kinda make sense. If AMD is already making the 32 core N2 Zen 6c CCD for server, why not combine the same CCD on the desktop with the desktop IOD and provide a 32 core part for desktop?

WCCF can't even properly quote their source, there is nothing in that chiphell post talking about Medusa Ridge.

fastandfurious6 · Mar 9, 2025

52core nova lake will be 100% outperformed by 24c zen6 lol. just core count

poke01 · Mar 9, 2025

fastandfurious6 said:
52core nova lake will be 100% outperformed by 24c zen6 lol. just core count

unlikely

IEC · Mar 9, 2025

If the chiplets are 75mm^2 or similar I expect excellent yields. And good availability.

Hulk · Mar 9, 2025

poke01 said:
So its likely R5 8C/16T, R7 12/24T, R9 24/48T

I think the 10700X might beat the 9950X in MT benchmarks. Could this be the first Ryzen 7 to beat the previous Ryzen 9?

To get from 12 to 16 you have to multiply 12 x 1.33. That's 33.3%. A big number. Now it is possible a smaller, lower power node may allow for higher sustained MT clocks, perhaps 10% better?

So now we're starting with 13.2 cores. That would mean that for equal performance Zen 6 would still need a 21% IPC boost. Not impossible but it's a lot. Assuming all 12 cores on on one CCD then there is some built in advantage vs 2 CCD's as well.

It is an interesting supposition. I'd bet that there will be some apps where Zen 6 really crushes it where this might occur.

dr1337 · Mar 10, 2025

OneEng2 said:
I wouldn't be surprised if things were more granular than that.

AMD isn't likely to make ANY CCD's less than 12c IMO (I could be wrong though). If that is the case, then:

Im personally in the camp of 16/32c for Zen 6 myself. Especially with a shrink onto 3nm going after more cores should be the lowest hanging fruit. But I do see another angle or two given the architecture of zen 5 where maybe they really do stay on 8c/16c CCDs.

First off Zen 5 was a much wider design compared to Zen 4, but had lower IPC improvements than expected. So maybe instead of caring about cores yet, AMD could go all in on refining Z5 with Zen 6 and adding a ton of transistors to help OOE and fill the current bottlenecks. And in a similar vein, if they improve GMI/packaging to allow cross CCD IO, we could potentially see a world where a 8c CCD + 16c CCD lack the issues we currently see between different CCDs and CCXs. Thus AMD can still ship a 24c halo product that always outperforms the 8-core gaming chips.

MS_AT · Mar 10, 2025

Hulk said:
I don't think Apple M runs Windows with very good IPC, right?. I don't give two sh*ts about Apple and their confounding and restrictive OS.

Well, x64 Windows yes, Windows on Arm? That is another story if you look at geekbench scores. Also your original post was about cpus not ecosystems. While I don't plan to buy Apple product myself, neglecting the achivements of other cpu design teams would be akin to what Intel did to land itself in its current poor state. Also Tenstorrent plans to release 16-wide RISC-V CPU by 2027 iirc. RISC-V has also variable lenght instructions if I am not mistaken. While it may turn out to be a dud at least the desgin team belives it is viable.

inquiss · Mar 10, 2025

OneEng2 said:
I wouldn't be surprised if things were more granular than that.

AMD isn't likely to make ANY CCD's less than 12c IMO (I could be wrong though). If that is the case, then:

2CCD's that yield perfect gets you 24c.

1CCD that yields perfect gets you 12c.

Some CCD's will yield 10c good on a CCD (they have to work in pairs) That gives you the potential for:

2CCD 20c

1CCD 10c

Some CCD's will yield 8c good on a CCD. That gives you:

2CCD 16c

1CCD 8c

A really bad CCD could yield only 6c on a CCD. That gives you:

2CCD 12c

1CCD 6c

Of course, the 2CCD versions will have double the cache so will perform better in some apps by a lot.

I don't know how AMD plans to slice this marketing mess though. Maybe 8 variants in core count alone is too much? Then imagine 3 frequency bins! Dizzying .

They'll get through it by mainly offering one SKU. Like today.

12 core vcache CPU. The rest for DIY is sort of irrelevant.

inquiss · Mar 10, 2025

Hulk said:
It is my opinion and I know many disagree with this. There is no more low-hanging fruit when it comes to single thread performance. There is only so much instruction parallelism that can be extracted from a sequence of instructions that have dependencies on one another. It's not a problem of figuring it out or adding more transistors. The problem is the code itself.

I would expect the next generation of cpu cores from AMD and Intel to show an average IPC increase between 5 and 15%. With my estimate being 10%. I know this will have a lot of people up in arms, what's the use? But this is just a reality of decreasing your distance to a wall by half with every step. We've been walking towards the wall for a long time and the steps are indeed very small at this point.

Making my post even more grim is the fact that clock speeds using conventional cooling also seem to have topped out.

Of course I will be happy to be proven wrong when Zen 6 arrives with a 20% IPC gain. I just don't think it will happen.

Where is left to go? Well, it is obviously better multi-thread performance which is exactly where AMD and Intel are headed.

Increased performance, assuming CPU manufacturers provide us with massive multi-threaded performance is going to be in the hands of software developers that will need to make use of this multi-threaded compute.

You could say this for every generation that has come and gone. Nowhere left to go, how do we increase IPC..and yet it still continues to happen. Frequency can't get any faster, and yet it continues to happen.

I'm not saying that both of these things scale forever in their current ways...but considering every time people have thought that both were ending, they haven't.

Stacking is a new way of scaling, for example. Better interconnects. Materials. Design libraries. They all have their own scaling and added up it makes a difference.

2nm TSMC nodes can use finflex for higher frequency. I'm expecting zen 6 to look a lot like zen3 where part of the increase in performance comes from a decent clock boost, though I've seen some here say that the boost will come lower down the power curve and so be a bigger impact to mobile.

OneEng2 · Mar 10, 2025

inquiss said:
You could say this for every generation that has come and gone. Nowhere left to go, how do we increase IPC..and yet it still continues to happen. Frequency can't get any faster, and yet it continues to happen.

I'm not saying that both of these things scale forever in their current ways...but considering every time people have thought that both were ending, they haven't.

Stacking is a new way of scaling, for example. Better interconnects. Materials. Design libraries. They all have their own scaling and added up it makes a difference.

2nm TSMC nodes can use finflex for higher frequency. I'm expecting zen 6 to look a lot like zen3 where part of the increase in performance comes from a decent clock boost, though I've seen some here say that the boost will come lower down the power curve and so be a bigger impact to mobile.

The difference being that in the past, transistor budget and power budget doubled every 18 months. It is quite easy to get a large boost when you have wider everything, and deeper everything, and more complex logic everything over the previous generation.

Today, we are seeing what? 15% higher density per generation? .... and even this only after 3 years. Additionally, the cost of going from one node to another is on an exponential curve, so that 3 years may soon look more like 6 years.

I could be wrong, but I think the days of big gains every generation are over for good.

DisEnchantment · Mar 10, 2025

I hope one thing for Zen 6 platform will come to fruition.
EPYC CXL.mem to come to DT.
Turin can interleave CXL and DDR memory regions already, so ideally GPU CXL device attached to the root can see the memory of the host.

Linux is getting patches for address translation for Zen 5. Hopefully this Zen 6 goes further in this direction

CXL Address Translation Support For AMD Zen 5 Sees Linux Patches - Phoronix

www.phoronix.com

With such a setup we could install 1 TB of DDR on CPU and let the GPU use all of that for some LLMs and other interesting use cases. Can turn your Linux PC to some LLM monster
Will not be the most performant but at least can run something interesting.

Hulk · Mar 10, 2025

inquiss said:
You could say this for every generation that has come and gone. Nowhere left to go, how do we increase IPC..and yet it still continues to happen. Frequency can't get any faster, and yet it continues to happen.

I'm not saying that both of these things scale forever in their current ways...but considering every time people have thought that both were ending, they haven't.

Stacking is a new way of scaling, for example. Better interconnects. Materials. Design libraries. They all have their own scaling and added up it makes a difference.

2nm TSMC nodes can use finflex for higher frequency. I'm expecting zen 6 to look a lot like zen3 where part of the increase in performance comes from a decent clock boost, though I've seen some here say that the boost will come lower down the power curve and so be a bigger impact to mobile.

I'm confused. Zen 4 to 5 and Raptor Cove to Lion Cove brought less than 10% IPC gains (a lot less for LC). Clocks were also stagnant. This is the latest data/generation, which support my low hanging fruit opinion.

We shall see if the next generation bring a 20%+ IPC gain and increased frequency. The last generation was only "cleaning up the edges."

I WANT to be proved wrong! I hate this reality.

Hail The Brain Slug · Mar 10, 2025

Hulk said:
I'm confused. Zen 4 to 5 and Raptor Cove to Lion Cove brought less than 10% IPC gains (a lot less for LC). Clocks were also stagnant. This is the latest data/generation, which support my low hanging fruit opinion.

We shall see if the next generation bring a 20%+ IPC gain and increased frequency. The last generation was only "cleaning up the edges."

I WANT to be proved wrong! I hate this reality.

Maybe it's pessimistic, but 20%+ IPC, clockspeed bump, and 50% core count increase seems like too much for one gen.

gdansk · Mar 10, 2025

Hail The Brain Slug said:
Maybe it's pessimistic, but 20%+ IPC, clockspeed bump, and 50% core count increase seems like too much for one gen.

Where is this 20% IPC coming from?
The slide which was accurate for Zen 4 said ~10%.

GTracing · Mar 10, 2025

Hail The Brain Slug said:
Maybe it's pessimistic, but 20%+ IPC, clockspeed bump, and 50% core count increase seems like too much for one gen.

Zen2 was 15% ipc, a 100% core count increase, and a clockspeed bump.

Nothingness · Mar 10, 2025

GTracing said:
Zen2 was 15% ipc, a 100% core count increase, and a clockspeed bump.

Yes, but things have changed: when you're starting from "low", it's much easier to progress by large leaps. When your uarch is solid and process doesn't provide a lot of improvements, you're bound to advance more slowly.

Hulk · Mar 10, 2025

GTracing said:
Zen2 was 15% ipc, a 100% core count increase, and a clockspeed bump.

Fruit was within reach without a ladder.

adroc_thurston · Mar 10, 2025

gdansk said:
The slide which was accurate for Zen 4 said ~10%.

Says >10% right there.

Hulk said:
Fruit was within reach without a ladder.

They are for Z6 too, it's a double shrink.

Hulk · Mar 10, 2025

Hail The Brain Slug said:
Maybe it's pessimistic, but 20%+ IPC, clockspeed bump, and 50% core count increase seems like too much for one gen.

I agree with 20% IPC increase being unrealistic.

50% core count increase is quite doable if transistor density/economics allow for it. As for clocks, we seem to have hit a barrier somewhere around 5 to 6GHz depending on loaded cores. Power and heat go through the roof. It can be done one a couple cores, but loading them all up presents problems with heat and degradation. Just ask Intel, they know all about it. Zen 5 will run 2 cores under load at 5.7 on an AIO cooler, but only 5GHz or so for 16 cores. Raptor Lake was similar but would hit 6GHz for a while, I mean until the silicon degraded due to getting 1.5+ Volts pumped into it. But hey? It was fun while it lasted, right? I had both a 13900K and 14900K running at stock and it WAS fun while it lasted. Eventually the joke was on Intel as they had to buy me out of both of them. Now I sit beside my sanely clocked and volted Zen 5.

The IPC increase is a MUCH more difficult problem to crack. They have been squeezing that orange for 50 years. There just isn't a lot of juice left.

The logical thing for AMD to do if they want to put the pressure on Intel is go for about 5 to 8% IPC increase, 16>24 cores at the top of the stack, and perhaps a bit better fully loaded core clocks if the process is a bit more efficient. So instead of hitting 5GHz under heavy load, perhaps 5.1GHz or something like that.

I realize this isn't super exciting but I think this is our reality. Actually 16 to 24 cores is pretty exciting for those of us that can use the increase in MT compute, especially if this is simply pop out the old CPU and pop in the new one.

Hulk · Mar 10, 2025

Really, I'm not trying to be contrarian just to be that way. I'm looking at last gen-on-gen and reading the future.

IPC increases are going to be hard to come by moving forward based on last generation improvements.

And really, I do want to be proved wrong as I love this merry go round of updates in the pursuit of ever more performant CPU's under my desk!

CakeMonster · Mar 10, 2025

16 to 24 cores with 12c CCD's is super exciting if you ask me, it will basically solve most of the core parking and thread prioritization issues that have plagued us lately. Most games and normal usage should fit just fine on 12 cores on one CCD, even if you leave stuff on in the background (and I always do).

Glo. · Mar 10, 2025

DisEnchantment said:
I hope one thing for Zen 6 platform will come to fruition.
EPYC CXL.mem to come to DT.
Turin can interleave CXL and DDR memory regions already, so ideally GPU CXL device attached to the root can see the memory of the host.

Linux is getting patches for address translation for Zen 5. Hopefully this Zen 6 goes further in this direction

CXL Address Translation Support For AMD Zen 5 Sees Linux Patches - Phoronix

www.phoronix.com

With such a setup we could install 1 TB of DDR on CPU and let the GPU use all of that for some LLMs and other interesting use cases. Can turn your Linux PC to some LLM monster
Will not be the most performant but at least can run something interesting.

Is this something akin to Memory Caching from Apple M4 and M4 architectures?

Question Zen 6 Speculation Thread

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