Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E012 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop & Mobile H&HXMobile U OnlyMobile H
Process NodeIntel 4TSMC N3BTSMC N3BIntel 18A
DateQ4 2023Desktop-Q4-2024
H&HX-Q1-2025
Q4 2024Q1 2026 ?
Full Die6P + 8P8P + 16E4P + 4E4P + 8E
LLC24 MB36 MB ?12 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15



Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)



 

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Doug S

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How does SOCAMM address this problem? It looks like it it provides more bandwidth than LPCAMM can.

What do you base that on? I haven't seen any bandwidth comparisons, and since they have a similar number of pins I can't imagine the bandwidth would be all that different.

The main thing this is doing is completely screwing the chances of LPCAMM going anywhere. With two incompatible standards it will be easier for companies to skip both and continue soldering down LPDDR. Thanks for nothing, Jensen!
 

adroc_thurston

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Jul 2, 2023
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The main thing this is doing is completely screwing the chances of LPCAMM going anywhere. With two incompatible standards it will be easier for companies to skip both and continue soldering down LPDDR.
One is DC, one is client tho.
SOCAMM is just an attempt to make 6400 Grace SKUs actually field servicable.
 
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Sep 5, 2022
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From what I read SOCAMM has more I/O ports compared to LPCAMM. It has 694 I/O ports, more than LPCAMM's 644 I/O ports. There’s also supposed to be denser electrical wiring on the substrate module to connect the memory chips on substrate to the motherboard of the GB300. Nvidia is working with all 3 memory manufacturers(Micron, SK Hynix, Samsung) to make it a standard. It’s only a matter of time before JEDEC adopts it as a standard for everyone.
 

AMDK11

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Jul 15, 2019
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The LionCove core itself is a reset if we are to strictly adhere to Intel's tradition in this matter.

It is a bit strange that the C&C analyses show that the predictor is also lame in some respects compared to RaptorCove, even though Intel claims that this part is 8x larger in some respects (whatever that means).
 
Jul 27, 2020
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even though Intel claims that this part is 8x larger in some respects (whatever that means).
I think Lion Cove was designed from the start for hyperthreading but they ran out of time to validate it and it was probably causing up to 8% lower ST performance in games so they decided to ditch it. Remember, Raptor Lake Refresh wasn't even supposed to exist. It should've been MTL-S, followed by ARL-S but their MTL-S experiment turned out really bad which impacted everything later on. It's super ironic that they call AMD a copycat but they ruined their consumer chips trying to copy AMD chiplet strategy. Should've kept mobile chips on chiplets and desktop chips monolithic.
 

511

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I think Lion Cove was designed from the start for hyperthreading but they ran out of time to validate it and it was probably causing up to 8% lower ST performance in games so they decided to ditch it. Remember, Raptor Lake Refresh wasn't even supposed to exist. It should've been MTL-S, followed by ARL-S but their MTL-S experiment turned out really bad which impacted everything later on. It's super ironic that they call AMD a copycat but they ruined their consumer chips trying to copy AMD chiplet strategy. Should've kept mobile chips on chiplets and desktop chips monolithic.
HT doesn't affect ST Performance also they Messed up the chiplet fabric hence the issue with MTL-S/ARL-S.

Chiplets are inevitable as for issues look at how AMD had issues with Ryzen Chiplets initially they were using Inferior chiplet Architecture to intel.
 
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Chiplets are inevitable
That's true but even Nvidia isn't getting into chiplets at the moment. Intel was arrogant enough to think that they could mimic AMD without any major issues. This is something Pat should've looked into and prevented them from doing.

Go slow and steady when embracing new manufacturing technologies. I thought that was established wisdom at Intel. Getting into chiplets with a brand new architecture, well, it's a miracle that ARL-S isn't much worse off than it already is. Gotta give Intel engineers that, though.
 

511

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That's true but even Nvidia isn't getting into chiplets at the moment. Intel was arrogant enough to think that they could mimic AMD without any major issues. This is something Pat should've looked into and prevented them from doing.
This is before pat Sapphire Rapids/Ponte Vehicco are Chiplets.
This time the Chiplet is not the issue as I have said before it is L3/NOC.
Go slow and steady when embracing new manufacturing technologies. I thought that was established wisdom at Intel. Getting into chiplets with a brand new architecture, well, it's a miracle that ARL-S isn't much worse off than it already is. Gotta give Intel engineers that, though.
It was never also if it was established practice at Intel we wouldn't have any of the major innovations with nodes.
 
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DavidC1

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Dec 29, 2023
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That's true but even Nvidia isn't getting into chiplets at the moment. Intel was arrogant enough to think that they could mimic AMD without any major issues. This is something Pat should've looked into and prevented them from doing.
It's brain drain that impacted them from doing anything right. They didn't/don't have the right people/team to do their jobs. Also, Meteorlake issues were way before Pat. It was impacted by 6+ month delay on 7nm.
Go slow and steady when embracing new manufacturing technologies. I thought that was established wisdom at Intel. Getting into chiplets with a brand new architecture, well, it's a miracle that ARL-S isn't much worse off than it already is. Gotta give Intel engineers that, though.
Lack of brainpower and chaos within the company is what caused Arrowlake issues.

Nothing would work well in that case, monolithic or not.

Intel was the leader in implementing the newest memory technologies and at fastest speeds. They led the world in density, frequency, and latency with SRAM. The Itanium 2 chip had massive 3MB L3 cache with a surprisingly high density and low latency.

Their designs were deficient even back then, but the implementation was solid. Mediocre design was made up by stellar process technology and excellent implementation.

Those guys are at Apple, AMD, and various other chip teams now.
Remember, Raptor Lake Refresh wasn't even supposed to exist. It should've been MTL-S, followed by ARL-S
Raptorlake itself wasn't supposed to exist. It was supposed to be Alder and then Meteor.
 

DavidC1

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Dec 29, 2023
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How does SOCAMM address this problem? It looks like it it provides more bandwidth than LPCAMM can.
SOCAMM seems to be higher cost than LPCAMM, and that comes with better specs, but it's really slotting between HBM and regular DDR memory.

You are still sacrificing performance with SOCAMM, since HBM is much higher bandwidth but you can't beat having multitudes of higher capacity either.
 

poke01

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Mar 8, 2022
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It's brain drain that impacted them from doing anything right. They didn't/don't have the right people/team to do their jobs. Also, Meteorlake issues were way before Pat. It was impacted by 6+ month delay on 7nm.

Lack of brainpower and chaos within the company is what caused Arrowlake issues.

Nothing would work well in that case, monolithic or not.

Intel was the leader in implementing the newest memory technologies and at fastest speeds. They led the world in density, frequency, and latency with SRAM. The Itanium 2 chip had massive 3MB L3 cache with a surprisingly high density and low latency.

Their designs were deficient even back then, but the implementation was solid. Mediocre design was made up by stellar process technology and excellent implementation.

Those guys are at Apple, AMD, and various other chip teams now.

Raptorlake itself wasn't supposed to exist. It was supposed to be Alder and then Meteor.

99.99% of these issues will be fixed with Nova Lake.
 
Jul 27, 2020
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Unless huge changes to a positive way is happening now, it won't be "fixed" for another 5 years on top of that.
The only thing they need to fix is the RAM latency and probably add a faster L3 with lower latency or reduce the L3 size to make it smaller/faster and add a larger L4 cache. 245K and 265K are pretty good for the price. 285K is kind of broken as it doesn't offer that much for the price bump.
 

511

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Jul 12, 2024
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The only thing they need to fix is the RAM latency and probably add a faster L3 with lower latency or reduce the L3 size to make it smaller/faster and add a larger L4 cache. 245K and 265K are pretty good for the price. 285K is kind of broken as it doesn't offer that much for the price bump.
265K was just $10 more expensive than than 245K few days ago 🤣
 
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DavidC1

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Dec 29, 2023
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The only thing they need to fix is the RAM latency and probably add a faster L3 with lower latency or reduce the L3 size to make it smaller/faster and add a larger L4 cache. 245K and 265K are pretty good for the price. 285K is kind of broken as it doesn't offer that much for the price bump.
They need *significant* reductions to get a noticeable improvement, which won't happen without better engineering.

I can believe being better by the time Nova Lake is out, but I wouldn't bet on being back to pre-2014 levels of leadership.
 
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