Discussion AMD SoC Halo series GPU discussion

MS_AT · Sunday at 9:30 AM

https://www.notebookcheck.net/GMKte...ty-of-Strix-Halo-EVO-X2-mini-PC.989734.0.html comparable pricing to framework.

Joe NYC · Monday at 10:47 AM

From MLID: he says that Medusa Halo can be 256 bit LPDDR5 or 384 bit LPDDR6, and either socket FP11 or FP 12.

Since socket FP11 is Strix Point package, it seems like AMD is planning on releasing backward compatible version of Medusa Halo for LPDDR5, but the new version will be 384 bit LPDDR6.

Kepler_L2 · Monday at 2:31 PM

Joe NYC said:
From MLID: he says that Medusa Halo can be 256 bit LPDDR5 or 384 bit LPDDR6, and either socket FP11 or FP 12.

Since socket FP11 is Strix Point package, it seems like AMD is planning on releasing backward compatible version of Medusa Halo for LPDDR5, but the new version will be 384 bit LPDDR6.

View attachment 120995

The LPDDR6 publicly available documentation clearly states that "Combo PHYS" are not possible, so support for LPDDR5 seems extremely unlikely.

adroc_thurston · Monday at 2:32 PM

Kepler_L2 said:
The LPDDR6 publicly available documentation clearly states that "Combo PHYS" are not possible, so support for LPDDR5 seems extremely unlikely.

they can do an RMB and TO two different SOC tiles tho.

Joe NYC · Monday at 3:18 PM

Kepler_L2 said:
The LPDDR6 publicly available documentation clearly states that "Combo PHYS" are not possible, so support for LPDDR5 seems extremely unlikely.

If the connection between the SoC and CCD is standardized, then it might be possible to sell Zen 6 CCD with Strix Halo SoC.

And this combo might be ready before the full Medusa Halo. It could also explain conflicting info on version of RDNA:

Strix Halo SoC + Zen 6 CCD would be 3.5
Monolithic designs could be 4.0 (from the diagram in the video)
Then later, full version of Medusa, in 2027, with LPDDR6 could have RDNA 5

ToTTenTranz · 2025-04-01T06:39:00-0400

Joe NYC said:
From MLID: he says that Medusa Halo can be 256 bit LPDDR5 or 384 bit LPDDR6, and either socket FP11 or FP 12.

Since socket FP11 is Strix Point package, it seems like AMD is planning on releasing backward compatible version of Medusa Halo for LPDDR5, but the new version will be 384 bit LPDDR6.

View attachment 120995

This is all over the place. There's no way AMD is still undecided about the RAM and GPU architectures for a chip taping out 8 to 10 months later.

coercitiv · 2025-04-01T09:27:01-0400

ToTTenTranz said:
There's no way AMD is still undecided about the RAM and GPU architectures for a chip taping out 8 to 10 months later.

It's not AMD who is undecided, it's MLID

adroc_thurston · 2025-04-01T20:57:06-0400

ToTTenTranz said:
There's no way AMD is still undecided about the RAM and GPU architectures for a chip taping out 8 to 10 months later.

hahahaha
hahahahahahah
hahahahaha yeah about that.
See AMD is notorious for keeping SOC config options afloat until the very last moment.
Like I don't know what core counts Venice gonna have in the end.

Joe NYC · 2025-04-02T00:14:24-0400

coercitiv said:
It's not AMD who is undecided, it's MLID

Having a mid-life upgrade, Strix Halo SoC + Zen 6, while maintaining FP11 compatibility, LPDDR5 compatibility and keeping Strix Halo RDNA3.5 SOC could be a possibility, if the full Medusa Halo is a 2027 product (with LPDDR6)

BTW, I have a weird feeling that AMD actually deliberately leaked (through MLID) the client Zen 6 roadmap as some sort of shock / awe / demoralization attack on Intel, tempting Intel to kill itself answering every single segment AMD is seeking to dominate. (And it seems like that what AMD might have designs for, on this roadmap).

Discussion AMD SoC Halo series GPU discussion

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