Discussion AMD SoC Halo series GPU discussion

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Joe NYC

Platinum Member
Jun 26, 2021
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From MLID: he says that Medusa Halo can be 256 bit LPDDR5 or 384 bit LPDDR6, and either socket FP11 or FP 12.

Since socket FP11 is Strix Point package, it seems like AMD is planning on releasing backward compatible version of Medusa Halo for LPDDR5, but the new version will be 384 bit LPDDR6.

 

Kepler_L2

Senior member
Sep 6, 2020
782
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From MLID: he says that Medusa Halo can be 256 bit LPDDR5 or 384 bit LPDDR6, and either socket FP11 or FP 12.

Since socket FP11 is Strix Point package, it seems like AMD is planning on releasing backward compatible version of Medusa Halo for LPDDR5, but the new version will be 384 bit LPDDR6.

View attachment 120995
The LPDDR6 publicly available documentation clearly states that "Combo PHYS" are not possible, so support for LPDDR5 seems extremely unlikely.
 

Joe NYC

Platinum Member
Jun 26, 2021
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The LPDDR6 publicly available documentation clearly states that "Combo PHYS" are not possible, so support for LPDDR5 seems extremely unlikely.

If the connection between the SoC and CCD is standardized, then it might be possible to sell Zen 6 CCD with Strix Halo SoC.

And this combo might be ready before the full Medusa Halo. It could also explain conflicting info on version of RDNA:

Strix Halo SoC + Zen 6 CCD would be 3.5
Monolithic designs could be 4.0 (from the diagram in the video)
Then later, full version of Medusa, in 2027, with LPDDR6 could have RDNA 5
 

ToTTenTranz

Senior member
Feb 4, 2021
387
752
136
From MLID: he says that Medusa Halo can be 256 bit LPDDR5 or 384 bit LPDDR6, and either socket FP11 or FP 12.

Since socket FP11 is Strix Point package, it seems like AMD is planning on releasing backward compatible version of Medusa Halo for LPDDR5, but the new version will be 384 bit LPDDR6.

View attachment 120995

This is all over the place. There's no way AMD is still undecided about the RAM and GPU architectures for a chip taping out 8 to 10 months later.
 
Reactions: marees

adroc_thurston

Diamond Member
Jul 2, 2023
5,385
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There's no way AMD is still undecided about the RAM and GPU architectures for a chip taping out 8 to 10 months later.
hahahaha
hahahahahahah
hahahahaha yeah about that.
See AMD is notorious for keeping SOC config options afloat until the very last moment.
Like I don't know what core counts Venice gonna have in the end.
 

Joe NYC

Platinum Member
Jun 26, 2021
2,946
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It's not AMD who is undecided, it's MLID

Having a mid-life upgrade, Strix Halo SoC + Zen 6, while maintaining FP11 compatibility, LPDDR5 compatibility and keeping Strix Halo RDNA3.5 SOC could be a possibility, if the full Medusa Halo is a 2027 product (with LPDDR6)

BTW, I have a weird feeling that AMD actually deliberately leaked (through MLID) the client Zen 6 roadmap as some sort of shock / awe / demoralization attack on Intel, tempting Intel to kill itself answering every single segment AMD is seeking to dominate. (And it seems like that what AMD might have designs for, on this roadmap).
 

Geranium

Member
Apr 22, 2020
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AMD intends Strix Point and other APUs of this class to be paired with their own GPUs. OEMs want those APUs to be pairedwith Nvidia GPUs. So AMD having choice of earning money for one product, over none always will pick earning money for one product, over none.
But does it really profitable in mid to long run? I dont thing so. Pairing a APU designed for thing and light sends wrong signal to consumers and decrease mind share. It also do not increase market share for Radeon. It is loss-loss situation for both AMD and consumers.

There is currently no Strix Point based laptop that can compete with Apple M4 based Macbook Pro for efficiency. And is to blame for this, not AMD as Strix Point in proper design is efficient; It is always the Nvidia loving OEMs.
 
Reactions: Joe NYC

LightningZ71

Platinum Member
Mar 10, 2017
2,083
2,533
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AMD shot themselves in the foot with strips point. They chased core count with a dual CCX design that didn't give them a massive MT boost while knowing they had a better solution for that market coming. They ditched their MALL cache for an NPU that's currently near useless. The iGPU improvement was not that great either.

In my personal opinion, I would have rather seen them stick with an 8 core Zen5P CCX with 16MB of L3, take the space that's saved by not having a second CCX, with it's L3 cache, and reshuffle the floorplan to allow for a 16MB MALL cache. Pay the price in area to have 2 more WGPs, giving 20CU total to better use the extra effective memory throughput. That would have been a much larger iGPU performance improvement.

What would you have? The same ST improvement, slightly lower total MT performance, but maybe better in some cases and still an improvement over HawkPoint in all cases. You'd have the same NPU. iGPU performance would be MUCH higher.
 

LightningZ71

Platinum Member
Mar 10, 2017
2,083
2,533
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If I wanted 4 P cores, 4 C cores, and HALF the iGPU, I would. I wanted more iGPU and generally better than Hawk Point in every way instead.
 
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