Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

DisEnchantment · Apr 24, 2020

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.

N7 performance is more or less understood.

This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

511 · Apr 5, 2025

fastandfurious6 said:
my prophecy

1) TSMC N3 -> N2 will be yuge difference

2) Apple @ N2 will come Q2 '26, AMD following soon after

3) intel 18A similar perf to TSMC N3 / N4
will get stomped by TSMC N2

Now
1) N3 -> N2 is 15% PPW improvement and 10-15% density Improvement it is less than Intel 4 to Intel 3 18% PPW performance jump and the density is in ballpark of 10% that Intel got 🤣 not to mention no SRAM Scaling how is this huge difference?
2) First N2 product will be an iPAD or iPhone imo.
3) 18A is N3P level according to TSMC CEO and I am pretty sure we can take that as a baseline.

OneEng2 · Apr 6, 2025

Josh128 said:
Nah, if 18A hits spec if will at least equal N2. N2 doesnt have backside power delivery, that should be a major boost for 18A, enough to offset anything it otherwise loses to N2 on.

BSPDN reportedly does allow more dense layouts; however, it doesn't seem to show up in the metrics. Additionally, BSPDN has more issues with hot spots than FSPDN.... so even if Intel gets a density improvement (over N2) there may be downsides as well.

LightningZ71 · Apr 6, 2025

If you have a lower clocked architecture, such as a fat ARM processor, then BSPD allows you to throw a ton of extra circuits at a problem instead of clocking to the heavens to achieve higher performance. Lower clocks generate less relative heat, ameliorating the hot spot issue to a degree.

Doug S · Apr 6, 2025

OneEng2 said:
BSPDN reportedly does allow more dense layouts; however, it doesn't seem to show up in the metrics. Additionally, BSPDN has more issues with hot spots than FSPDN.... so even if Intel gets a density improvement (over N2) there may be downsides as well.

I've been thinking about this and I wonder if that really matters for phones. They already have "hot spots" in the SoC since there isn't any way to get the heat off it other than passive radiation to other components.

There have been rumors that Apple is going to add some sort of vapor / phase change setup like some Androids have to the Pro iPhones next year. Going from basically no heatsink to something like that should compensate for any increased tendency to form hot spots. Yeah I know N2 doesn't have BSPDN, but since A16 is basically N2+BSPDN maybe it will be ready in time for Apple to skip N2 and go directly to BSPDN. Before they renamed N2+BSPDN "A16" TSMC's plan was to introduce N2, then a variant of N2 with BSPDN six months later.

maddie · Apr 6, 2025

LightningZ71 said:
If you have a lower clocked architecture, such as a fat ARM processor, then BSPD allows you to throw a ton of extra circuits at a problem instead of clocking to the heavens to achieve higher performance. Lower clocks generate less relative heat, ameliorating the hot spot issue to a degree.

BSPD allows higher power delivery. Is it useful or cost effective for lower power circuits?

511 · Apr 6, 2025

maddie said:
BSPD allows higher power delivery. Is it useful or cost effective for lower power circuits?

BSPD is not cost effective for Mobile Phone SoC it is already reaching $240 for a flagship N3E SoC Price BSPDN will just add to costs.

Doug S · Apr 7, 2025

511 said:
BSPD is not cost effective for Mobile Phone SoC it is already reaching $240 for a flagship N3E SoC Price BSPDN will just add to costs.

That's not the actual cost, that's the cost with Qualcomm's markup. You get around 600 100mm^2 chips per wafer. So at the rumored $30K price for N2 that's $50 per chip, or $55 assuming you get 90% yield. Yes there's testing/packaging etc. but that's relatively independent of the process (or at least won't increase much between N3 and N2 and shouldn't increase at all between N2 and A16) So even if BSPDN adds 15-20% to wafer cost that's only $10 more per chip. Don't forget that BSPDN should reduce die size a bit you might go from 100mm^2 to 95mm^2 for the same design done with BSPDN, meaning more chips per wafer which reduces the per chip cost increase.

That's why Apple is willing to pay for newer processes without complaint - they can afford another $10 for the SoC every couple years when a new process generation hits. They can make it up by saving money elsewhere (hello Apple C1 modem) or increasing base prices by $50 or $100 every few years.

Qualcomm is also fine with absorbing that cost, but to maintain their margins if their cost goes up by $10 they probably increase the price they charge OEMs by $30. Of course as the spread between chip manufacturing cost and chip purchase price increases, it makes it more attractive for companies to go their own way like Google, or seek out lower margin competitors like Mediatek. Probably one of the reasons why Samsung has continued investing billions to try to fix their foundry, the savings from making Exynos SoCs instead of buying Qualcomm SoCs is significant, especially in lower end phones. Though I suppose nothing except pride stops them from making Exynos SoCs at TSMC.

adroc_thurston · Apr 7, 2025

511 said:
BSPD is not cost effective for Mobile Phone SoC it is already reaching $240 for a flagship N3E SoC Price BSPDN will just add to costs.

yeah it is it's literally an area scaling trick.
Where it sucks is high-power desktop since you're bonding a wafer on top of the hot-hot xtors.

511 · Apr 7, 2025

adroc_thurston said:
yeah it is it's literally an area scaling trick.
Where it sucks is high-power desktop since you're bonding a wafer on top of the hot-hot xtors.

It scales area but it increases Metal Layers as well also it negatively affects SRAM see the Total layers went from 15+RDL to 18+RDL more layers add to cost .

Now to Sram as you can see it basically increased area by 10%

https://twitter.com/x/status/1892250305796173971

Doug S said:
That's not the actual cost, that's the cost with Qualcomm's markup. You get around 600 100mm^2 chips per wafer. So at the rumored $30K price for N2 that's $50 per chip, or $55 assuming you get 90% yield. Yes there's testing/packaging etc. but that's relatively independent of the process (or at least won't increase much between N3 and N2 and shouldn't increase at all between N2 and A16) So even if BSPDN adds 15-20% to wafer cost that's only $10 more per chip. Don't forget that BSPDN should reduce die size a bit you might go from 100mm^2 to 95mm^2 for the same design done with BSPDN, meaning more chips per wafer which reduces the per chip cost increase.

Even if they would win on cost the next problem would be hotspot how would you cool it on mobile phone considering they are passively cooled most of the time?

adroc_thurston · Apr 7, 2025

511 said:
It scales area but it increases Metal Layers as well also it negatively affects SRAM see the Total layers went from 15+RDL to 18+RDL more layers add to cost .

Everyone is bumping metal stacks for frequency anyway.
BSPDN is a win with no losses.

511 · Apr 7, 2025

adroc_thurston said:
Everyone is bumping metal stacks for frequency anyway.
BSPDN is a win with no losses.

Mobile guys aren't though last I checked in HPC sure

adroc_thurston · Apr 7, 2025

511 said:
Mobile guys aren't though last I checked in HPC sure

They sure are, you should check the Cu counts on Apple stuff.
Enlightening I tell you.

511 · Apr 8, 2025

adroc_thurston said:
They sure are, you should check the Cu counts on Apple stuff.
Enlightening I tell you.

Got a link?

oak8292 · Apr 8, 2025

Speculation on my part. Intel’s 18A is quite a bit more expensive per transistor over N2. It has an additional layer of GAA with four layers of gates and BSPD. N2 is three levels of GAA and does not require wafer thinning, a second support wafer and TSVs for power. Intel’s process design looks like it is optimized for Intel’s high frequency ‘performance’ design with higher currents. The BSPD should also increase consistency in frequency with less binning.

The N2 design will have less current capability but also less capacitance and potentially lower leakage, meaning better for low power, low cost designs. This is essentially what TSMC continues to focus on. Who and how many customers adopt 16A will be interesting. Also whether there continues to be an option without BSPD for the next complimentary FET designs.

511 · Apr 8, 2025

oak8292 said:
Speculation on my part. Intel’s 18A is quite a bit more expensive per transistor over N2. It has an additional layer of GAA with four layers of gates and BSPD. N2 is three levels of GAA and does not require wafer thinning, a second support wafer and TSVs for power. Intel’s process design looks like it is optimized for Intel’s high frequency ‘performance’ design with higher currents. The BSPD should also increase consistency in frequency with less binning.

The pricing of 18A/N2 should be within ballpark of eachh other.

oak8292 said:
The N2 design will have less current capability but also less capacitance and potentially lower leakage, meaning better for low power, low cost designs. This is essentially what TSMC continues to focus on. Who and how many customers adopt 16A will be interesting. Also whether there continues to be an option without BSPD for the next complimentary FET designs.

It is something only time can tell

Win2012R2 · Apr 9, 2025

511 said:
The pricing of 18A/N2 should be within ballpark of eachh other.

With Intel Fabs also getting 59% gross profit margin?

511 · Apr 9, 2025

Win2012R2 said:
With Intel Fabs also getting 59% gross profit margin?

The profit margin on nodes is dependent on volume the more you pump the better you get but initial ramp is always costly.

For Gross Profit Margin no I would say it would be decent margin not TSMC Margin though

Win2012R2 · Apr 9, 2025

511 said:
For Gross Profit Margin no I would say it would be decent margin not TSMC Margin though

How can you possibly know that?

dullard · Apr 9, 2025

511 said:
The pricing of 18A/N2 should be within ballpark of eachh other.

Maybe not. Trump just announced a 100% tariff if TSMC doesn't build in the US. If that tariff goes through, then 18A would be about half the price of N2. https://www.reuters.com/world/us/tr...pay-100-tax-if-it-doesnt-build-us-2025-04-09/

Win2012R2 · Apr 9, 2025

dullard said:
If that tariff goes through, then 18A would be about half the price of N2.

No, it won't be because it does not have 100% of all parts used made in the US from scratch. Chips in tray are easy to smuggle too in large quantities

511 · Apr 9, 2025

Win2012R2 said:
No, it won't be because it does not have 100% of all parts used made in the US from scratch. Chips in tray are easy to smuggle too in large quantities

The wafer price would double though but this is impossible to do in less than 3 years

dullard · Apr 9, 2025

Win2012R2 said:
No, it won't be because it does not have 100% of all parts used made in the US from scratch. Chips in tray are easy to smuggle too in large quantities

I thought we were talking about the cost per transistor of nodes. So that is machine time + silicon cost + labor/overhead only. At least some of Intel's silicon comes from the US (and thus not subject to the whole tariffs) but certainly not all. But the machine time is what is really the cost driver as nodes get smaller. Sure, chips packaged in a tray are a different thing. But still, the biggest cost of that is the processed silicon itself.

Which companies do you expect to be smuggling in TSMC chips?

maddie · Apr 9, 2025

511 said:
The wafer price would double though but this is impossible to do in less than 3 years

3 years? I wonder if its understood the immensity of replicating an industrial ecosystem from scratch. Starting with "does the educational system even exist to produce the quantity of technically skilled staff needed to operate these companies?".

oak8292 · Apr 9, 2025

dullard said:
Maybe not. Trump just announced a 100% tariff if TSMC doesn't build in the US. If that tariff goes through, then 18A would be about half the price of N2. https://www.reuters.com/world/us/tr...pay-100-tax-if-it-doesnt-build-us-2025-04-09/

A big issue that I see with U.S. tariffs is the percentage of products for tech companies that are sold in the U.S. Apple may be a U.S. based company but only about 30% of their products are actually sold into the U.S. Most Apple products never touch the U.S. It may mean that Americans are buying products on older nodes until TSMC completes fabs for the node in the U.S.

iPhones will definitely be cheaper overseas. If Apple has to revamp their supply chain to the U.S. at higher cost they will lose a lot of global marketshare to foreign (Chinese) smartphone manufacturers.

Doug S · Apr 9, 2025

dullard said:
Maybe not. Trump just announced a 100% tariff if TSMC doesn't build in the US. If that tariff goes through, then 18A would be about half the price of N2. https://www.reuters.com/world/us/tr...pay-100-tax-if-it-doesnt-build-us-2025-04-09/

No he said he "threatened" them with a 100% tariff unless they increased their investments in the US, and is crediting that for their recent announcement of building more fabs in the US.

Of course given the length of time it takes to build and equip a fab they could easily choose to slow walk some of that and wait for his term to end. With all the chaos caused by the on again off again tariffs there's zero certainty for huge investments that involve materials and components from all over the world, which they could site as the reason for delays - probably increases the odds of such a wait him out strategy.

Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

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