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  1. R

    Discussion Apple Silicon SoC thread

    According to Kurnal's composite image, it looks like the R1 is 3 active tiles, 6 embedded silicon passives, and 8 dummy tiles. The smaller tiles flanking the main tile look like memory dies, and the d2d interface looks an awful lot like UltraFusion. So probably bumped InFO-LSI again, or possibly...
  2. R

    Discussion Apple Silicon SoC thread

    The entry level M2 Max Studio dissipated up to 145 W, while the fully equipped M2 Ultra version could pull 295 W. The highest power consumption for an M3 Max in a laptop isn't necessarily the highest power draw for an M3 if you were to let it off the leash. But you can't just stack two SoC dies...
  3. R

    Discussion Apple Silicon SoC thread

    I wonder if the R1 was bumped (InFO/CoWoS) or bumpless (SoIC)? Regardless, it was Apple's first crack at a truly disaggregated design with 11 tiles, although I'm not sure all of them are active.
  4. R

    Discussion Apple Silicon SoC thread

    Meanwhile, I only recently acquired an A to C cable, because I wanted to back up some older computers that didn't have Type-C ports to a portable SSD and didn't trust the dodgy, not even remotely to spec adapter that came packed in with the SSD. How did you end up with a dozen A to C cables and...
  5. R

    Discussion Apple Silicon SoC thread

    The M-series chips have integrated SSD controllers that use PCIe lanes for transport between the SoC and the NAND packages. Each package supports two NAND channels and is connected to the host by a single PCIe Gen4 lane. The M1/2/3/4 have 2 PCIe lanes dedicated to SSD functions and support up...
  6. R

    Discussion Apple Silicon SoC thread

    I will. It'll probably look very similar to the current M2 Pro Mac mini. The only difference will be that the SSD interface will be limited to the equivalent of two PCIe Gen4 lanes and probably 2GB capacity due to the lower number of channels. I don't see any reason why Apple would omit the...
  7. R

    Discussion Apple Silicon SoC thread

    USB4 is based on Thunderbolt 3, however there are minor differences in signaling rate, encoding, and tunneling protocols. Thunderbolt interoperability is optional for USB4 devices. In other words, you can in fact make USB4 hosts / devices that will not work with Thunderbolt 3 hosts / devices...
  8. R

    Discussion Apple Silicon SoC thread

    So while I agree that the 24-inch iMac design is stupid in so many ways and represents a major regression from the Intel based iMacs, Apple has never made a Mac without a headphone jack: I also think a lot of people use dongles because they don't realize that Type-C ports are still USB ports...
  9. R

    Discussion Apple Silicon SoC thread

    I think something may have gotten lost in translation with the Geekerwan "overclocked" comment. LPDDR5X is just higher clocked LPDDR5. Micron makes no distinction between the two in their datasheets, parts catalogs, and part numbering schemes. From teardowns, we've seen the part numbers for the...
  10. R

    Discussion Apple Silicon SoC thread

    You can't expect me to notice something that obvious. 🤣 Based on that, I measured 13.10 mm x 12.71 mm = 166.5 mm², which is right in the same neighborhood of what y'all came up with already. The Thunderbolt and PCIe blocks are super easy to pick out. I didn't spend much time on this, so...
  11. R

    Discussion Apple Silicon SoC thread

    How are y'all getting die size estimates when this is the first N3E chip, uses different libraries (2-1 finFLEX and 3-2 finFLEX), and is based on new microarchitechtures? What feature sizes are you using to determine scale? GPU cores? I wouldn't be surprised if die size did increase given the...
  12. R

    Discussion Apple Silicon SoC thread

    Lol! Reading quickly through the thread I thought I saw SMT, but it was SME. Totally different, disregard.
  13. R

    Discussion Apple Silicon SoC thread

    The plot thickens! Those multicore scores are pretty competitive with GB6 multicore scores for Snapdragon X Elite under Windows (Linux are still higher): https://browser.geekbench.com/v6/cpu/search?dir=desc&page=1&q=Qualcomm+Oryon&sort=multicore_score Doesn't look like SMT came into play with...
  14. R

    Discussion Apple Silicon SoC thread

    If you're referring to me, I don't know for certain, and none of us probably will until the folks that are willing to dig into stuff like that have devices in hand. But the probability is high enough that I'm willing to take it for granted at this point. edit: Never mind, I see you were...
  15. R

    Discussion Apple Silicon SoC thread

    Looks like TrendForce / DRAMeXchange (part of TrendForce) published slightly ahead of AnandTech, so maybe that's where Ryan got the number from? But they also said the memory clock speed of M4 only reaches about or approximately 7700 MT/s. Which is odd because 7500 is a bog standard bin for...
  16. R

    Discussion Apple Silicon SoC thread

    Here's that M4 iPad result vs. the top scoring M3 iMac with 16GB of RAM (I figure the 24-inch iMac is essentially a big iPad with a stand anyway): https://browser.geekbench.com/ml/v0/inference/compare/364912?baseline=372975 Interestingly, the CPU speed for that M4 result is only 3.93 GHz vs...
  17. R

    Discussion Apple Silicon SoC thread

    Interestingly, this is the first M-series launch where Apple hasn't given us a die shot, so we can't even compare the cores visually. It's been the rumor for a while now that all of the iPhones 16 will be getting the A18. Apple is doing a tick-tick-tock to navigate the N3 transition. iPhones...
  18. R

    Discussion Apple Silicon SoC thread

    There's a typo in the chart there, the memory should be LPDDR5X-7500 not 7700. 128 x 7500 / 8000 = 120 GB/s. edit: I realize it's Ryan's chart, not yours.
  19. R

    Discussion Apple Silicon SoC thread

    Yeah, I like how Apple had to get out ahead of the people doing teardowns who will go, "Derp, Apple's new $3000 iPad Pro doesn't even have a heat sink!" by explaining their thermal solution during the product launch. iFixit seems to have no idea that the black film that Apple has been using for...
  20. R

    Discussion Apple Silicon SoC thread

    Seems legit. M2 was Avalanche + Blizzard on TSMC N5P, while M3 was Everest + Sawtooth on N3. So you have µarch plus process improvements with that generation. Apple claimed the Everest performance cores in the M3 were up to 15% faster than Avalanche in the M2, and the Sawtooth efficiency cores...
  21. R

    Discussion Apple Silicon SoC thread

    Just a quick note on binning. The M3 generation saw the heaviest binning to date by Apple, which was completely to be expected given the situation with the N3 node. The binned version of the M3 had 2 out of 10 (1/5) of the GPU cores disabled, which is a lot more die area than a single...
  22. R

    Discussion Apple Silicon SoC thread

    Oh, and iPad Pro orders immediately after event, available next week on Wed 5/15. So this was a proper launch for the M4.
  23. R

    Discussion Apple Silicon SoC thread

    M3 had AV1 decode as well, I think. Although it was never in an iPad.
  24. R

    Discussion Apple Silicon SoC thread

    The M4 is almost certainly based on the A17 Pro and uses the same Everest and Sawtooth CPU cores, which were also in the A16 Bionic and M3. The GPU core is probably the same as the A17 Pro and M3. It looks like that was one of the few things that got pulled forward for the M3 or bumped to the...
  25. R

    Discussion Apple Silicon SoC thread

    LPDDR5X-7500, so they stopped short of the LPDDR5X-8533 that I had predicted. The M4 Pro and Max will certainly follow suit, but could potentially go higher than the M4. Disabling a p-core makes no difference to single-threaded performance, and two additional e-cores plus the power and...
  26. R

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    Have the Arrow Lake-U CPU tile and Panther Lake GPU tile been mentioned publicly, or is that just stuff you know / have shared here? I mean it's good that there are some internal client designs on Intel 3 (assuming those are Intel 3 and not Intel 4), but those are both pretty tiny chips, so...
  27. R

    Discussion Apple Silicon SoC thread

    The reason I believe my measurements are more accurate is because the source image that @Frederic_Orange started with is problematic. It's not really a photo of a wafer, it's a screen capture of an animation taken from the Apple keynote. That might be an undoctored yet dramatically lit video of...
  28. R

    Discussion Apple Silicon SoC thread

    My initial estimates based on the die images provided by Apple and measurements of IP blocks shared with the A17 Pro were as follows: M3: 12.64 mm x 10.67 mm = 135 mm² M3 Pro: 12.69 mm x 14.96 mm = 190 mm² M3 Max: 20.40 mm x 21.03 mm = 429 mm² I'm pretty sure these are a lot closer than the...
  29. R

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    Well, clearly Intel wasn't planning on packaging Meteor Lake in a facility that wasn't even going to be finished until a year after the intended launch date. But also, my bad regarding Fab 42. MTL was actually being assembled at CH4 in Arizona, which is a much smaller facility. They showed this...
  30. R

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    Is Intel actually packaging constrained, or just demand constrained for MTL? Fab 42 in Arizona is where they were doing the MTL packaging, and it's huge. Even complex packaging like MTL should take way less time and space than processing wafers. The only thing I can imagine being a constraint is...
  31. R

    Discussion Apple Silicon SoC thread

    We're definitely getting into the weeds here, but several of these numbers were brought up in relationship to whether or not a new SoC introduced at the event on Monday could be manufactured on N3E or not. While there is no conclusive answer to that question, there are some very clear upper and...
  32. R

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    Just to put it in perspective, Intel currently has enough fab capacity to crank out 180 million MTL 6+8 CPU tiles in the next 12 months, enough to put one in every low-power x86 device sold in a typical year, while operating their fabs at 60% capacity and with defect densities of 0.25 / cm²...
  33. R

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    Intel D1X Mod3 in Oregon and Fab 34 in Leixlip, Ireland are both fully tooled up with EUV equipment and supposedly in high-volume production using the Intel 4 process. At an estimated capacity of 12 kwpm for D1X and 22 kwpm for Fab 34, that's a combined 34 kwpm of Intel 4 capacity. Per Mizuho's...
  34. R

    Discussion Apple Silicon SoC thread

    Maybe not. Apple does these types of spring launches because the announcement might not fit into the WWDC keynote, or they want to get the products out ahead of the conference. I think this is true on both counts with these new iPads. Too much to talk about, and a lot of it isn't focused on...
  35. R

    Discussion Apple Silicon SoC thread

    What you say is true, but WWDC is announced well in advance because people are traveling from all over the world to attend in person, and it's a multi-day event focused on developer relations, not new hardware launches. They just use the keynote for that purpose because so many people watch it...
  36. R

    Discussion Apple Silicon SoC thread

    You are correct, six months isn't set in stone. However, because EUV litho steps take significantly longer than DUV, the more EUV layers the process incorporates, the longer the cycle time. Cycle times for N3 are brutal. Some analysts were claiming 4 months. N3E is a bit better, but still...
  37. R

    Discussion Apple Silicon SoC thread

    If you go even further down the codename rabbit hole, the A17 Pro was "Coll" and the M4 is supposedly "Donan"—both Scottish islands. So A17 Pro = Coll = T8130 and M4 = Donan = T8132. Now the codenames don't necessarily indicate that both SoCs share all of their IP blocks, but it does suggest...
  38. R

    Discussion Apple Silicon SoC thread

    M3 had the same CPU cores as A17 Pro *and* A16—they all use Everest and Sawtooth. That's sort of the problem with inferring too much from the SoC identifier here. The A-series repeated CPU microarchitectures while the M-series appeared to skip over the A16 generation, so the SoC IDs aren't...
  39. R

    Discussion Apple Silicon SoC thread

    I highly doubt Apple will call whatever is in the new iPad Pros "M4", but if they do, it would be kinda stupid because it is just another Everest / Sawtooth SoC on TSMC N3. N3E didn't enter volume production until Q4'23, so products shipping before June is highly unlikely, and I doubt Apple is...
  40. R

    Discussion Apple Silicon SoC thread

    Hmmm... not seeing any UltraFusion D2D on this shot of the M3 Max. Unless that image is cropped, it looks like there won't be an M3 Ultra based on that die. I don't recall ever seeing a Palma 2C codename anywhere either. Source: @techanalye1 on X: Also surprised nobody seems to be talking...
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