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  1. N

    Discussion Mediatek SoC thread

    Sorry I wasn't clear: I was talking about A72 not A53.
  2. N

    Discussion Mediatek SoC thread

    Are you sure of that? The private (but coherent) L2 is mandatory IIRC.
  3. N

    Question CPUs for shared memory parallel computing

    Out of curiosity, is any of the SW you use available on Intel macOS (I mean recent versions)?
  4. N

    Discussion Qualcomm Snapdragon Thread

    And yet people think Arm Ltd cores are seriously underperforming the competition. Yeah definitely. But the score of X925 isn't that far behind in SPECint.
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    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    I count that as corporate culture :)
  6. N

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    Complacency and corporate culture.
  7. N

    Discussion Qualcomm Snapdragon Thread

    Little. Qualcomm cancelled the only device I was considering to run Linux, the dev kit. Laptops are different beasts, and running an OS not supported by the vendor laptop can make the device a displeasure to use (this also applies to x86 laptops). And I won't even talk about running Linux on a...
  8. N

    Question Geekbench 6 released and calibrated against Core i7-12700

    Why would that be Skymont given that it also leads in ST?
  9. N

    Question Geekbench 6 released and calibrated against Core i7-12700

    What is worth looking at for compilation workloads are the results of the clang test.
  10. N

    Discussion Qualcomm Snapdragon Thread

    I agree. OTOH the difference should not be massive. I don't expect a significant amount of vectorized code in SPECint 2017 except for x264.
  11. N

    Discussion Qualcomm Snapdragon Thread

    After a few iterations of the same microarchitecure everything that brings performance with acceptable power and area is picked, because the uarch usually has reached a balanced point where more performance requires larger changes and these are done earlier in the design cycle. So, yes, if the...
  12. N

    Discussion Future ARM Cortex + Neoverse µArchs Discussion

    Thanks a lot! I won't claim I understand the generated R-V code, but it looks similar to the AArch64 one.
  13. N

    Discussion Qualcomm Snapdragon Thread

    And yet people draw conclusions after seeing variations of a few percents. I think I already explained how this is done during CPU development: extracts of benchmarks/apps or instruction traces are run through simulation (accurate model, RTL simulation, FPGA, emulator) in a completely...
  14. N

    Discussion Qualcomm Snapdragon Thread

    Yeah but some of the tests almost do scale linearly (in particular the rendering one). Not all, far from it, and that's why the global score can be misleading.
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    Discussion Future ARM Cortex + Neoverse µArchs Discussion

    Cf. an example in the post above. My general vector knowledge is limited, so I might be off, but to me it looks VL agnostic in that simple example.
  16. N

    Discussion Future ARM Cortex + Neoverse µArchs Discussion

    This looks VL agnostic, doesn't it? https://godbolt.org/z/8K57957nT I will leave to someone more knowledgeable than me to add the proper RISC-V flag to enable vector code generation.
  17. N

    Discussion Apple Silicon SoC thread

    Gnome3 is an abomination. If you don't add a dozen of extensions it is just plain horrible.
  18. N

    Discussion Qualcomm Snapdragon Thread

    Got it and it makes sense. I wonder how much one would leave on the table by having TSO always on; perhaps there's some way to test the on Apple or Qualcomm machines?
  19. N

    Discussion Apple Silicon SoC thread

    Wait for SPECv8.
  20. N

    Discussion Apple Silicon SoC thread

    That's exactly what happened to me. When I get lost, I can open a terminal and be presented with a shell and commands I'm familiar with. My main issue is to remember to properly use cut and paste instead of relying on the middle button of my mouse 😅
  21. N

    Discussion Apple Silicon SoC thread

    No, I am just closer to retirement than most in my circles 😁
  22. N

    Discussion Qualcomm Snapdragon Thread

    Arm memory ordering model is different from x86. That's why Apple added an extension to help Rosetta2. Yeah Arm is different from x86 beyond decoders 😉
  23. N

    Discussion Qualcomm Snapdragon Thread

    Qualcomm complaining about anti-competitive behavior, funny.
  24. N

    Discussion Qualcomm Snapdragon Thread

    The architecture license doesn't exclude core royalties as far as I know.
  25. N

    Discussion Apple Silicon SoC thread

    Coming from 35 years of UNIX, I had few issues when switching to macOS a few months ago. OTOH I have never been able to properly use/tweak/fix Windows, despite having it on my PCs for 25 years. Well except for launching games, which is why I like to call it a gaming OS (which it is for me).
  26. N

    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    And then you have to thank Intel for segmentation by removing extensions.
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    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    You made a clear expostion, thanks 😀 I would add that AArch64 is not that RISCy anymore. The architecture manual is more than 14k pages long and there are hundreds of instructions, and dozens of extensions. Though it obviously has roots in RISC principles (single size for instruction encoding...
  28. N

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    I clearly specified SPECint in my original quote 😉 I was not trying to say that AArch64 was better or equal in all cases contrary to the OP that claimed that x86-64 requires less instructions. This is simply not always correct and C&C results clearly demonstrate it. Even in SPECint you can see...
  29. N

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    I could explain but given how stubborn you are I will save my time. Go read Realworldtech.
  30. N

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    A respected reviewer shows data on a very well known benchmark and you show two instructions used before a syscall? And insist on having demonstrated x86-64 needs less instructions in general? Really? If you have any knowledge of programming, go play with https://godbolt.org/ and learn a thing...
  31. N

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    Confronted to the reality of a dozen of different benchmarks, you provide a two lines example. That's interesting.
  32. N

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    This is incorrect. https://chipsandcheese.com/p/running-spec-cpu2017-on-chinese-cpus Talking about SPECint 2017
  33. N

    Discussion Future ARM Cortex + Neoverse µArchs Discussion

    It's still faster than NEON: https://code.videolan.org/videolan/dav1d/-/commit/01558f3f6609b750f6a850960119bec9e8fbe018
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    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    Hmm I don't see any APX in there. What am I missing?
  35. N

    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    I am wondering. I would have expected parallel compilation to benefit a lot from SMT.
  36. N

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    I don't know about Blender, but some other renderers certainly benefit from AVX-512: https://www.phoronix.com/review/amd-zen5-avx-512-9950x/3
  37. N

    Question Intel and AMD form x86 Ecosystem Advisory Group

    It's quite likely JHH and Haas still have discussions and some common interests, just like Intel and AMD have, but thinking JHH has some form of control from behind the curtain over Arm through Haas (don't read this out loud at work :D) is certainly exaggerated. Anyway enough of that, let's get...
  38. N

    Question Intel and AMD form x86 Ecosystem Advisory Group

    Streaming SVE operates at vector length of SME, so in the case of Apple that's 512-bit. But it's so slow it's useless (except for tasks between two matrix operations). The thing is that you have a single SME block per cluster (these matrix engines are large), so 4 CPU with SVE might be faster...
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    Question Intel and AMD form x86 Ecosystem Advisory Group

    IMHO SVE2 adoption is no better on Arm. Thanks to Qualcomm. And to Arm CPUs for not bringing enough benefits to switch from NEON 128-bit to SVE2 128-bit. At least it can be argued that all Arm customers of recent CPUs have SVE2, but still. OTOH I wonder if Arm isn't more advanced with security...
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