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  1. S

    Intel says 32 nm on track for late 2009

    Hey, I resent that! :) I co-authored paper 3.4 in the Microprocessor Technology session (Dynamic Frequency-Switching Clock System on a Quad-Core Itanium Processor). But yeah, the conference did turn out to be much more university-heavy than usual.
  2. S

    Nehalem: AMD's design!

    Eh, maybe I'm just a cynic because I focused on architecture in grad school and had switched to circuit design by the time I finished because architecture opportunities in the industry are rare. But I'm definitely not the only person that feels this way...keeping in mind that I consider "new"...
  3. S

    Nehalem: AMD's design!

    Hell, the nCUBE/2 had an integrated DRAM controller and I/O fabric (with 14 links supporting up to 8096 processors)...in 1991. :) And as far as core microarchitectures, most of the really exciting stuff was established in IBM's mainframes in the 60s. Honestly, there's not much architecturely...
  4. S

    Why are the CMOS process sizes set the way they are?

    I'm not an expert, but despite that Intel, AMD et al develop their processes independently, they do contract out to third-parties for tools and equipment. Having standard node sizes decreases the cost in using third-party equipment. Long channel fets are common in analog and tricky circuits...
  5. S

    Can some explain the difference between Digtal and Analog Circuits?

    ??? I never said that analog IC is dead. On the contrary, I do mixed signal design in another area that requires a lot of analog components, microprocessor clock system design. However, the fortune cookie was extremely unusual, no?
  6. S

    Can some explain the difference between Digtal and Analog Circuits?

    Funny story: Not too long ago, I was at lunch at a Chinese restaurant with people from work. When we got our fortune cookies, one of my coworkers got a fortune that read (I'm not kidding) "Digital circuits are made of analog components". We figure that a disgruntled, laid-off analog IC engineer...
  7. S

    Infinate AMD processor speed?

    Making a processor work at some target frequency requires more than just making circuit paths operate faster...timing is more complex than that. Latches (or flip-flops, depending on the methodology used) are sequencing elements that "store" values at the boundaries of pipeline stages...for...
  8. S

    processor size, features, and speed...why do they limit themselves?

    Actually, the power density of the L3 cache in Montecito is extremely low...the 24 MB L3 consumes less than 5% of the total chip power (4.2 Watts). There are large opportunities for power reduction in higher-level caches using architecture and circuit techniques. Just so that Patrick doesn't...
  9. S

    RAID 1 for your CPU and memory?

    Yep, it's often called lockstep. IBM's G4-G6 processors (no relation to IBM's PowerPC G5 or Motorola's G4) in their zSeries mainframes have dual pipelines that execute the same instructions. At the end of checkpoint periods, the state of the two pipelines are compared, and if they mismatch...
  10. S

    CPU caching scemes...

    Caches can be blocking or non-blocking...a non-blocking cache allows multiple requests to be issued, and can service and complete misses out-of-order. The issue at heart is determining, as data come back out-of-order, which data is for which request. They're pretty important to performance for...
  11. S

    itanium 2 with 24 mb cache?

    "Only the paranoid survive." Intel has numerous contingency plans...more than a year or two out, the roadmap gets hazy. These are the questions only time will resolve. :) I don't know about mainstream rendering apps, but Itanium 2 reportedly excels at raytracing...benchmarks with POVRay have...
  12. S

    itanium 2 with 24 mb cache?

    Transistor per transistor and die area per die area, cache is much "cheaper" than core logic, from a basis of design effort, power consumption (static and dynamic), and performance ROI. Cache has a transistor density close to 10x higher than core logic, especially for higher-levels of cache...
  13. S

    VLIW Processors - Transmetta

    OOOE universally refers to the "second-generation" superscalar processors that can execute instructions that occur later in the program order that others. The processors I mentioned, among others, are always called in-order. In-order processors do not need to support re-ordering; they are...
  14. S

    VLIW Processors - Transmetta

    PA-RISC is a sequential RISC architecture...the current PA 8x00 series is an out-of-order implementation. The Itanium 2 core pipeline is relatively simple...this is the opinion that I've heard many times from other architects and circuit designers on my team who have had long experience with...
  15. S

    future cpus: x86 to EPIC possibilities?

    Sure we do branch prediction. :) Itanium 2 has a rather sophisticated two-level local history branch predictor, with a large dedicated branch history backing store, return stack buffer, and perfect loop predictor.
  16. S

    different approach to dual processing

    Yes and no...there isn't a distinct x86 core on Itanium 2, but there is a x86 front-end which, in combination with the IA-64 back-end, provides full hardware x86 compatibility. I'm told by people who would know (I'm on the team that design McKinley, the 1 GHz Itanium 2) that you could boot into...
  17. S

    different approach to dual processing

    What you're describing isn't so easy. The Pentium core's circuits likely wouldn't even function correctly if ported to the 860 (130 nm) or 1262 (90 nm) process, and there's absolutely no way it would meet the timing required for the end-of-life frequency targets for the 130 nm and 90 nm Itanium...
  18. S

    Who's going to produce the first dual-cored CPU?

    Don't believe everything you read online. I don't want to hijack the thread, we can discuss this off-line via pm if you want.
  19. S

    Who's going to produce the first dual-cored CPU?

    Publically announced plans and private roadmaps are two separate issues. The first dual-core Itanium, Montecito, has taped out for introduction next year (I'm on its circuit design team). Intel's COO, Paul Otellini, showed off a wafer of Montecitos a month ago at a analyst conference. To give...
  20. S

    Apple releases new Dual G5 2.5 GHz Power Mac

    I agree, I would never base purchase decisions on SPEC CPU, although I do use a few of the programs in the integer suite (Perl, gzip, gcc). It's purely an academic exercise for me....though I can guarantee, regardless of what processor you use, SPEC CPU was used to test the effect of design...
  21. S

    Apple releases new Dual G5 2.5 GHz Power Mac

    :confused:I'm not denying that, I partially agree. I'm talking about testing methodology, not who's to blame for the P4's performance on gcc. Normalizing the compiler is simply not in the spirit of the SPEC CPU test: "These benchmarks measure the performance of the processor, memory and...
  22. S

    Apple releases new Dual G5 2.5 GHz Power Mac

    My point is that claiming fairness can't be made if a compiler produces better code for one microprocessor than another. Using the same compiler removes the front-end optimizations as a variable in the tests, but back-end code generation is perhaps even more important for performance...if the...
  23. S

    Apple releases new Dual G5 2.5 GHz Power Mac

    And gcc has historically produced poor code for the Pentium 4, even using P4-specific flags (though it may have improved). The fact that gcc was first developed for and is widely used with x86 does not mean that it produces good code for any x86 microprocessor...code scheduling is a more of a...
  24. S

    Apple releases new Dual G5 2.5 GHz Power Mac

    Accord's comment is fair, using the same compiler does not necessarily "level the playing field" across platforms. The back-end code generation and scheduling, different for each architecture and microarchitecture, is rather crucial for performance and may not be ideal for a particular...
  25. S

    Apple releases new Dual G5 2.5 GHz Power Mac

    Just a nit-pick, the P4's 128 rename registers cannot be called GPRs, they are not accessable to software. Your understanding is off on rename registers vs. logical (architected) registers. Having a pool of physical renaming registers that is larger than the number of logical registers is...
  26. S

    Out of Order fetch

    Out-of-Order Instruction Fetch using Multiple Sequencers. And at the other end, Deconstructing Commit (an exploration of out-of-order instruction commit and a reorder buffer implementation).
  27. S

    RISC vs. x86

    Well, strictly speaking, this isn't possible on Itanium. The instruction operation is defined by both a 4-bit opcode in each instruction, in addition to the template...you can't look at the instruction alone to determine what it does. Assuming that this wasn't the case, it's likely easier to...
  28. S

    RISC vs. x86

    The template isn't necessarily for decoding purposes, but for instruction dispersal, when instructions are assigned to issue ports. Allowing any instruction to issue to any issue port will increase the fan-out on most of the instruction buffer slots by quite a bit. Keep in mind that most...
  29. S

    RISC vs. x86

    I'd hesitate to call MP Opterons "SMP", even though the name has become synonomous with multi-processing, as the memory access is not uniform across processors. Except for some early experimentation with multi-level trees and crossbar links, SMPs have almost exclusively been shared buses...
  30. S

    RISC vs. x86

    Are you referring to classic VLIW or Itanium? On Itanium, that's not true (of course, an abundance of parallelism may still be limited by instruction rates on both superscalar and VLIW/EPIC). Independent instruction groups, containing no RAW or WAW dependences, are not per 128-bit instruction...
  31. S

    RISC vs. x86

    I think the best way to approach RISC vs. CISC is to look at the historical trends. Back in the 60s and 70s, the high-performance processors were multi-chip with slow main memory (eg core memory). Going to memory was an extremely expensive operation, so instruction bandwidth was at a premium...
  32. S

    Intel to Kill off P5 / Tejas

    Huh? AMD has had a strong presence in the retail desktop market for a long time. They surpassed Intel in retail desktops in 1999: Link
  33. S

    New Dual-core opterons to be pin-for-pin compatible

    Yep...the HP PA-8800 and Sun UltraSPARC IV, both dual-core processors and released earlier in the year, are drop-in compatible with existing system designs. The dual-core Itanium coming out next year will be as well.
  34. S

    8 way processor vs. 4 way processor in regards to SQL

    Really? The enterprise benchmarks tell otherwise...let's look at TPC-C. Results using 1.5 GHz Itanium 2: Unisys ES7000 Aries 420 Enterprise Server (16-way): 309036.53 TpmC NEC Express5800/1320Xd (32-way): 577530.77 TpmC (+87% over 16-way) HP Integrity Superdome (64-way): 1008144.49 TpmC (+75%...
  35. S

    Intel's gamble on high-speed computer chip [Itanium] not paying off

    I'm not a journalist. If one is going to write an article about the state and future of Itanium, the facts that Accord99 and I brought up are rather important, wouldn't you agree?
  36. S

    Intel's gamble on high-speed computer chip [Itanium] not paying off

    A few other things to consider: - Dean Takahashi, one of the authors of the article, is a well-known Sun cheerleader. Casting Itanium as a technology that customers don't want or need in the first paragraph is hardly a good start for a fair article. For crying out load, he quotes Sun's CEO...
  37. S

    Article: Dell has no plans to use AMD chips

    1.18 million Xeon servers left port in Q3, over 100X that of Opteron. That's why people were raising their eyebrows when AlexWade said that Opteron is outselling Xeon. And the Itanium market is definitely growing, and fast. IDC reported that Itanium server shipments grew over 70% in Q2...
  38. S

    Intel x86-64. **Updated 2/17** It IS AMD64 compatible...out next quarter

    You mean Intergraph. That lawsuit was overturned in favor of Intel in the appeal.
  39. S

    Apple releases dual 90 nm (66 mm2 die size) 64-bit G5 2.0 GHz Xserve 1U with ECC support *Pix*

    You have to consider the systems, which is going to affect the markup quite a bit...switch from a v440 to a v480 (both capable up to 4-way), and a 4-way system with nearly identical specs (save the addition of an 8 MB external cache on the v480, but with the loss of 80 MHz in clockspeed and a...
  40. S

    Apple releases dual 90 nm (66 mm2 die size) 64-bit G5 2.0 GHz Xserve 1U with ECC support *Pix*

    There have been a number of big-name engineering apps ported to Windows on IPF...the type of people who would use them are those that do mechanical CAD, CAE, visualization, EDA (electronic design automation), etc. Thus far HP has been the only supplier of IPF workstations, and given their...
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