MSRs (model-specific registers) exist and companies like Intel or AMD only document some of them for external use. Some configuration values may exist in on-chip read-only memories, but a lot of them can be overridden with different values on boot-up from the BIOS or even from the OS via...
Yes, and it's another way that the benefits of server chip development continue to trickle downmarket into the desktop space. Four cores at 65W means eight cores at 130W! Not to mention it enables nifty quieter, more mobile systems in the space most of us care about.
Oh, indeed. I see a...
Well, perhaps not if the replacement components have the exact same specifications. But the point of new design projects that aren't "dumb" shrinks is that they're not simply re-implementing the same circuits with smaller transistors, they're actually changing the functionality and capability...
Well, maybe. I'd love to be proven wrong on that. But even if every piece of the design has been used before, the whole is still a never-before-combined gestalt that has to be tuned and tested and debugged. Previous tunings pretty much have to be thrown out because of all the inter-component...
Glad you liked them. And thanks for the video pointer; I have not seen that before! And yes, without Netburst's failure against the Athlon64, Intel would not have implemented 64-bit x86 or tick-tock!
I'm eagerly waiting to read that reply. ;)
... what an ignorant thing to say. I don't know of many people at all who could possibly have more experience in examining different engineering solutions in the computing world than the gatekeeper of code contributions to the Linux kernel. I think it's fair to say that if it hasn't passed...
As other people have said, Intel tried with the Pentium 4, and even with non-x86 architectures like the iAPX 432 and Itanium, and those turned out to be dead ends. That's not to say various parts didn't eventually make it into later designs. But there's always risk in creating a new...
I love all the uarch diagrams and die photos y'all have assembled. That's great stuff, and I love just staring at them. Kudos!
This is a bit of a Ship of Theseus question, isn't it? When every component of a design has been replaced piecemeal over the years, is it really the same design at...
The majority of the desktop and mobile market gains no performance going above 4 cores, and it actually hurts power efficiency. Only niche applications benefit from it, and it's going to cost you niche prices. Back in 2006, Dadi Perlmutter, Executive Vice President and General Manager of Intel...
You rang? ;)
Sounds like y'all could benefit from reading up on the differences between multithreading approaches that a processor core could implement. Paul Demone wrote a good treatment in his RealWorldTech article on what was planned for the Alpha EV8 chip. Jon Stokes of ArsTechnica wrote a...
Not much, other than if implemented correctly, the IME should have no impact at all on performance during normal operation. Really, it's like adding another independent watchdog component that operates in parallel with the existing chip components. So the entire premise of the thread is...
Yup. It's not just your CPU/chipset firmware you have to worry about, it's your storage component firmware as well. The guys at libreboot and these security outfits that make futile recommendations are pretty much screwed, because no modern hardware sold since 2008 meets their requirements for...
I dunno, but would they need to add a fourth physical ALU if that were the case? Why couldn't they just issue port 6 int ops to one of the original ALUs on port 0 or 1, if they weren't going to implement the full forwarding network?
There's some great information in there.
So, some highlights:
- Improved branch prediction
- Same pipeline length as Sandy Bridge -> branch misprediction penalty is the same
- Parallelized cache misses to reduce latency
- Deepened out-of-order buffers to provide a larger instruction window
-...
You may question it, but Intel's declared intent is that the processor is going to become an "increasingly smaller part" of the die, to make room for graphics and other system functions, as we move towards an SoC market...
No one knows when Steamroller for the desktop will be released. Those chips haven't been announced. We don't even know if it will use the same socket AM3+ as Vishera. The desktop chip roadmaps list Vishera lasting through 2013.
The speculation is that the first we'll see SR is in...
If you listen to the keynote, it was also all about Llano, and GCN. Trinity was announced, the way Steamroller and Excavator have been announced, but nothing about its microarchitecture was revealed there.
That's not what you were saying before.
And the Steamroller slides also describe...
Fact check: AMD did not reveal anything about Trinity or Piledriver at HotChips 2011... in fact, they presented more about Llano and Bulldozer there. I notice you failed to provide a link for HotChips 2011, so here it is: http://www.hotchips.org/archives/hc23
So yes, AMD seems to be jumping...
But... isn't the CPU itself fast enough for most people? As long as AMD is still making better GPUs, I think Intel will be devoting die space to outdoing AMD. Hooray competition!
I don't know if we'll hear much about Broadwell at the September IDF; it appears to be all about Haswell. It...
And by the same token, the more things change, the more things stay the same. ;) Some things remain fundamentally unchanged. RAM capacity has been following Moore's Law, doubling every couple of years, but the number of cores that software uses has not been increasing anything like...
http://slashdot.org/story/06/07/27/1753255/intel---market-doesnt-need-eight-cores
"Two are enough for now, four will be mainstream in three years and eight is something the desktop market does not need. ... I want everybody to go from a frequency world to a number-of-cores-world. But especially...
I think this is the first good news for AMD CPUs I've heard in way too long. This guy Keller seems to have had a hand in everything good AMD has produced. We might not see the results for a few years yet, but it shows that AMD still intends to invest long-term in their CPU products.
I didn't recall "must be touch-based" to be part of the definition of an Ultrabook. :P
Seriously, I think all of the Ultrabooks released so far have been the more conservative designs. It looks like Intel is trying to shake up things by encouraging more tablet/laptop hybridization and...
I didn't recall "not touch-based" being part of the definition of an Ultrabook.
http://www.tomshardware.com/news/intel-q22012-ultrabook-ivy-bridge,16336.html
That was Vernor Vinge and the technological singularity. Which is a fun idea to play with in science fiction, but I'm somewhat doubtful that it's actually possible.
Ha. Somehow I don't think that'll fix all of Bulldozer's problems. Generally, the main problem with Bulldozer is that it's produced by the resources available to AMD.
Anyway, just posting to say that it's the L1 data TLB that's being doubled in Piledriver, not the data cache. The Translate...
Not necessarily. It is more than possible to have higher utilization, but more variable IPC. Utilization is a measure of how occupied a CPU's resources are; IPC is more relevant to customer needs in that it measures only useful work done. Two examples of ways in which a CPU could keep its...
That's obviously not what was intended. Microarchitects have a perfectly fine term for the concept you are using, which is "utilization". Since they didn't refer to it in those terms, that indicates that what they meant was "performance per clock".
Heh, yes. The text does seem to give the impression of schizophrenia based on conflicting editorial goals. Still, it seems to me that "IPC has decreased slightly" is the least obscured fragment of the statements there, and the rest of the "maintain IPC" verbiage shows a lot of redactional...
Thanks Dresdenboy, that's exactly what I was telling Abwx. Also, in multiple quotes of Mike Butler around the web, the phrase "hold the line" was used to express the same goal.
http://techreport.com/articles.x/21813/1...
Um, he doesn't say anything of the sort. You can always get an admissible table of any radix if you choose M, N and k large enough. In fact, Russinoff gives a formula for phi(i, j) on page 11! Just plug in rho=4, choose M, N, and K, test the inequalities he gives for all entries and if they...
But here's where you misunderstand the results. The theorems only prove correctness of a divider algorithm; they do not necessarily apply to any physical dividers which could implement the algorithm in different ways. There's no evidence that Intel relied on the 2005 "theorem" (now known to be...
I wasn't trying to discredit them. I am trying to discredit you and what you're trying to imply. :P
I have no doubt David Russinoff does good work. I was merely pointing out that his results don't actually apply to any processors you might have thought would answer the question
Hm, that is not what is in my paper. This is the exact sentence, which you misquoted:
So, you did not copy it as it was written; you dropped two words and punctuation which caused my search for the text I sourced from you to fail, and you added a parenthetical comment which was not in the...
You can't draw that conclusion. First of all, your "quote" from the paper does not appear in the paper, and second, in the absence of first-hand reports from the Penryn designers, the paper can only make suppositions about the proof methods that Intel may have used. Given that this divider has...
Well, you know, there was a lot of forum speculation that Intel had to have known about the issue ahead of time to have announced and shipped a Cougar Point fix within a month of announcing the recall. So there you go, that conspiracy theory has more legs!
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