So here's the story on IPC from my perspective.
The original design goal was higher IPC. Back before we had taped out the first processors the discussion came up. I am not allowed to say anything in public that hasn't been vetted past engineering. I specifically asked the engineering...
Benchmarks at launch, like I said.
I am pretty sure that when we launch, both sides in the fanboy war will gear up. Everyone will have their own pet benchmark that proves their point. A year after launch the fighting will still be going on. Not because it matters but because some people...
I have never understood why people get so emotional over things.
If the product is right for you, you buy it. Pretty simple.
That rant reminds me of this: http://www.youtube.com/watch?v=kHmvkRoEowc
1. Let's not.
2. Crap, someone took my slide and changed the titles but did not bother to change the numbers at the bottom.
Phenom has 6 cores, each can handle a 128-bit FP execution which is 4x32. that should be 6x4=24. Magny Cours has 12 cores or 12x4=48.
I will retract the 6282...
If they were official AMD numbers they would be on AMD.com
That is my slide. 128-bit FP is today's SSE.
No, that is a server slide (I made it) and that refers to the current 12-core Magny Cours.
Actually, I think that you are a.) overestimating the impact of sharing resources and b.) undersestimating the impact of Turbo CORE.
If you load 4 threads on 2 modules there is a small impact from sharing, probably between 0 and ~10%, depending on the workload. However, there are also...
My thought is that 90% are fake and the other 10% are not representative of actual performance. Trying to draw any conclusions on performance, in light of how many fakes are out there is impossible.
But you keep going back to AVX-256. Are we talking about client or server. I don't expect to see that anywhere on the client side and only rarely on the server side.
You are aware that FP pipelines are really long, right? And that if you mix AVX and SSE, intel needs to clear the pipeline...
If you think that there is somehow a problem in FP-heavy applications, I'd love to understand how that is.
Each module has a dedicated FP scheduler. The intel architecture does FP scheduling from a shared integer/FP scheduler. The integer thread, the hyperthread and the FP execution all...
How much wiggle room?
You'll know when you don't get a chip next time.
I would assume it is not worth the risk.
All of the press guys at AMD for the overclocking event had NDAs that said you cannot say anything until the press release went live.
How many of them posted anything...
We never get to month or week granularity, only quarter. The only time that I have taken it to month granularity is when it is the 3rd month of the quarter and we have promised to launch in that quarter. At that point there is no beating around the bush.
Here is how NDAs work: You sign a document saying that if the company gives you the product, you will not disclose any info about it until the date that the embargo lifts. Period.
Anyone is free to break the NDA, it is a civil contract, not a criminal offense.
However, you only get to do...
~95% of what you see out there in launch dates and benchmarks are fakes, so if you wave off everything, you are right 95% of the time.
My comment was that if we released benchmarks, I would *probably* have heard about it, but that is not 100% the case.
I am sure that we did a demo, but...
If you want to copy that thread and post it here (so people don't shoot off to another site) I am fine with that.
That post was my rant after a long week and a mexican martini at trudy's. Feel free to plagerize, as long as you don't change the text, have at it.
No, just a typo. Benchmarks that did not come from AMD will not be representative.
No to your second question, I don't comment on client products and really don't comment on dates.
OK, my rules for everyone:
1. No benchmarks that show up before launch will be representative of actual performance
2. No benchmarks that don't come from AMD will also not be representative
3. Anyone selling bulldozer before launch probably does not have it
All of this stuff is a...
It comes down to the serial vs. parallel tasks.
Let's say you are making a salad. 2 chefs can split that task, one chops the lettuce, one cuts the carrots, etc.
Now, take that low level task like chopping a carrot. That is a singular serial task. You've seen the chef shows where the...
I have addressed the 40% claim several times. In memory stream performance we were ~40% faster. In 4P performance, we were 40%+ faster. Where that got wrapped around the axle was people taking statements out of context and applying them to client parts, it was a server statement.
Server...
No, I am not saying that.
What I am saying is that someone on this thread is getting completely wrapped around the axle on one aspect and given the two choices (argue about it or wait until benchmarks are out) I would choose plan B.
I am not implying that at all, do not put words in my mouth.
Intel provided this info at IDF 2010. Session ARCS004 by Pallavi Mehrotra
In the presentation on slide #8 he explained how when running AVX-128 the top registers (128-256) are all padded with zeroes. This means that a 128-bit...
They will do that because Sandybridge has an issue with handling mixed SSE and AVX instructions. They need to clear out their pipeline between switching instructions, and this takes clock cycles. they recommemded at IDF that companies convert all SSE instructions to AVX-128 to avoid...
Most of the apps today that utilize any FP code are doing SSE 9128-bit). Most of that is not fully utilized.
The world splits into lightly-FP and FP-centric. In the light-FP world (probably 90% of the apps, including things like Excel, games, etc.) 128-bit FP is fine for them. They convert...
1. Don't harass nemesis on english. I spend half of my life in countries that don't speak english, it's a big world, everyone needs to deal with it.
2. Don't get all wrapped around instructions, what people are calling them and how they are documented. The days of instruction lockout are...
We are working with all of the compiler verndors to ensure that AMD processors can run AVX code. I can't speak to their tools (that is there business) but we have had no complaints nor issues with PGI, GCC, Microsoft, etc.
I can't speak for intel, but if their compiler doesn't support AVX on...
So, would you buy an AMD processor if we had the fastest $2000 processor, but at your price level intel was faster?
People don't buy based on the race track, they buy based on what they need.
All of this is pretty immaterial.
Everyone is thinking that a.) somehow economics are tied to performance (but 95% of the market or more is not buying on raw performance) and that b.) somehow die size and transistor counts are crucial.
The reality is that there are 2 kinds of...
It is variable but the max is the max. So all core boost would default (in your case) to 3.5GHz, but it you were near the top of your power budget it might drop to 3.4GHz instead of dropping back to base.
I use my frequent flyer miles to book my vacations (I fly ~150K+ miles per year, so...
On the client side you have an ecosystem ready to go because CPU+GPU already makes sense for 100% of the the client applications. And GPU compute is starting to catch the wave.
On the server side, GPU compute is something for HPC and other niches like specialized financial applications...
Yes, turbo is tied to TDP only so it will be much more consistent. Core count an clock speed are highly correlated. I do not have the frequencies in front of me to know how that carries through to boost frequencies. Every processor will have 3 speeds: base, all core boost and max turbo boost.
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