"Other than being noisy" doing a lot of work there :p
Decent $30-50 coolers perform much better than both the Wraith Max and Prism, never mind the Spire. The Stealth is infinitely better than Intel's stock coolers because it can actually keep the bundled CPUs within spec, but it was very loud...
Unlike Cinebench, 720p@360hz is an actual real world scenario if somewhat niche :)
Would be nice to see AMD closing the gap in high fps gaming because that's pretty much the last bastion where Intel is strictly superior.
I'm not to worried about getting data into the caches, games loop over reasonably small data sets every frame with relatively small changes. You can see the impact cache has on memory bound games in the difference between Zen1 and Zen 2 in something like CSGO.
Don't have to take the long way to memory if you hit the L3. It's harder to predict how much the unified L3 contributes compared to a straight up increase in cache size but I wouldn't be surprised if that's the single biggest upgrade in gaming benchmarks, even with the rumoured IF speed increase.
Desktop chips *are* server chips for Ryzen and the time frames don't match for a product released late this year. The only way this rumour would make sense for me would be if it's actually Zen3 APUs and the 4000 series bit is a misunderstanding.
Edit: that or Zen+ style update maybe.
CCX is still 4 cores but the L3 is now shared by the two CCX on the die.
New AAA titles are still going to be built around this console gen for a good while. I would be surprised if AMD did away with 6c/12t budget options, especially with how popular the 3600 ended up being.
Apple's cpus are a great example of this, A12 has double both L1 caches of Skylake X and 6x the L2 and targeting higher clockspeeds would require much worse latencies.
It would be impressive but also absolutely necessary to match Intel's pace. Ice Lake might be stuck on a dud node but clock for clock it's still the fastest x86 cpu.
On the bleeding edge 22nm process node ;)
I thought the endurance on high performance MRAM was still pretty poor but it's been a while since I've paid attention.
1. What are you going to be using your pc for and what's the tradeoff? If it's mostly for gaming and a 3600 will let you put more budget towards a GPU then that's probably the way to go, else the 3700x is looking real good.
2. How much do you value silence? Aftermarket cpu coolers won't reduce...
Yeah, I think we'll see a similar pricing structure to the 2XXX series for 8 cores and under, with the dual chiplet ryzen pricing overlapping low-end threadripper slightly. Mockingbird's pricing guesses feel pretty on point to me.
The IO die is almost exactly the same size as Summit Ridge with both CCX lopped off (~123mm2 vs 213 - 88 = ~125mm2) so I think we we can pretty safely put the eDRAM rumors to rest.
The article you linked measures the maximum power draw with POV-Ray which uses AVX2 instructions while CB doesn't. Intel has always let AVX2/512 workloads run out of spec and the power draw numbers aren't indictive of general use.
This is a silly both-sides-ism.
I mean, I would love to see the latency numbers cause de-integrating the mem controller is a bold move but a) it's way too early and b) the result would be meaningless for the vast majority of users who will be GPU limited anyways.
I also want a pony for my birthday but expecting a full suite of benchmarks 5-6 months ahead of launch is a bit unrealistic when they don't even have the final silicon yet.
Cinebench mimics a real world workload and scales well enough that the results can be extrapolated to other CPU-heavy tasks pretty reliably. It's also well-known and has a massive database of results. You propose they instead use a CPU limited gaming scenario where the results are by nature...
Some of the earlier roadmaps had "Zen+" as a seperate step between Zen and Zen2 implying that the 14nm+ products would also receive architectural improvements but this was dropped pretty early on. Sadly, the Zen+ moniker stuck around and colored the perception of Pinnicle Ridge.
Dedicated GPUs aren't a good comparison, since those are likely pad limited. Looking at the Raven Ridge die shot, I'd guess at 40-50mm2 for just the CUs.
I'm kind of torn on this because you'd think that the iGPU would benefit from a die shrink, but having more than ~12CUs seems like a massive...
I would be inclined to agree if not for a single detail. There's a reasonably good chance that the MCM layout could let AMD ditch the interposer requirement and hook up a 1Hi HBM chip to the iGPU through two IF links.
Alright, let me put it this way: I am skeptical that lower main memory access...
Yeah, while I'm inclined to think that the whole chiplet is a singular core complex, I don't think AMD has said anything about that. Though the PCI-E link stuff seems like a misinterpretation arising from the slides being very vague.
Besides demolishing 9900K in benches, there's a price point between top end mainstream and low end enthusiast that they could fill reasonably well with 12 to 16 core parts. Think 400-750$ for a theoretical R9 line.
Where has AMD stated this?
You can have low range parts using a single chiplet AND high end parts using two chiplets without incurring heavy costs. That's the whole point of the design, folks!
Y'know and manufacturing costs from being able to minimize the die size on a new process. And being able to bin and reuse those dies across the whole product stack. And being better able to optimize for frequency with most IO spun off to a seperate die. And being able to provide semi-custom...
I feel like y'all are talking right past Atari2600 while arguing about the evils of communism 8core R3s.
AMD can literally cover the entire consumer desktop range while only using the basic building blocks of a CPU chiplet, IO hub and GPU chiplet. CPU chiplet + IO, 2 CPU chiplets + IO, CPU +...
I've only seen Ryzen 2 used in clickbait articles.
Calling Pinnacle Ridge Zen+ implicitly hints at architectural improvements and I think AMD putting up the same core with iGPU and a Devil's Canyon-esque die shrink as the second generation just makes it more confusing for anyone not obsesivly...
I'll try to untangle this mess of a post.
Zen is the name of the architecture. The next iteration of the Zen architecture was called Zen+ in the earliest roadmaps but later renamed Zen 2. Zen+ isn't a thing anymore, but the tech community has appropriated this name for the 12nm die shrink of...
I agree, CAS values would be way more useful, the memory controller would usually hide some of the latency when hitting the same bank twice, as far as I understand. CAS latency is calculated in clock cycles so even if it was equal between HBM and DDR4, the former would take about twice as long...
The memory bandwidth is definitely going to be a bottleneck. RX 550 has a similar shader throughput with ~3x the memory bandwidth and the 50W TDP includes 4GB GDDR5 so it's not as apples to oranges as it might seem at first glance.
As for HBM, using it instead of DDR for system RAM would...
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