Does this apply to *any* Optane drive (ie: even consumer one), or it is an enterprise-specific feature? In other words: do the M2 version and Optane 905 provide full powerloss protection, similar to the X4800?
Thanks.
My questions: being byte-addressable, is power loss protection required on Optane drives? If so, why? Does the controller buffer use data? Any chances to have smaller, m2 drives with powerloss protection?
If not required, why the Enterprise Optane drives have supercap?
Mmm... while the Barton core was a very well executed product (I owned two Barton: a 2500+ @ 2100 MHz and a 2800+ @ 2500 MHz), the best P4 were faster than AMD chip.
See here for detail: http://www.anandtech.com/show/1117
Anyway, the price/performance ratio of Barton Athlon XP 2500+ was...
Other very interesting test can be read hear:
http://www.overclock.net/t/671977/hyperthreading-in-games
The bottom line probably is that, according to Termie's tests, on dual core processor Hyperthreading do a measurable positive difference in games performance.
On the other hand, with 4...
@Termie: Very good, interesting post.
This is right, but an ever worse problem is when processing two thread produce resource trashing on the shared structures (eg: cache, uop cache, ecc.): http://ixbtlabs.com/articles3/cpu/ci7-turbo-ht-p1.html
To reduce this problem, with any new...
I perfectly understand that Ironlake was Arrendale's GPU. What I mean is that
while current iGPU from Intel are way better than Ironlake-class ones, they remain way slower then competition in many games.
3DMarks and famous tripe-A games are a little better, as they enjoy a considerable...
It depends on the specific game being tested. Here you can find techreport's review: http://techreport.com/review/23662/amd-a10-5800k-and-a8-5600k-trinity-apus-reviewed/4
The same review shows that Pentium-class CPU are generally way slower then Trinity and Corei3s.
Regards.
You are right: K6 was the Socket7-compatible version of Nx686, developed by Nextgen. AMD did the smart move of acquire Nextgen at the right time.
For K7, they hired an almost-complete CPU design team from DEC.
Today AMD has many talented engineers, but Intel has _multiple_ talented...
Hi,
while current iGPU from Intel are way better than Ironlake-based design (GMA X3100/GMA4500), they seems to heavily suffer with complex geometry. Take a look at Civ5 late game: even a HD4000 is 3x slower than Trinity.
In not-AAA game the situation is somewhat similar, with lower then...
Hi,
while I can see your point, I think that the Pentium G620 is a too much handicapped chip. Any Core-i3 or A10 5700K should generally be preferable.
Regards.
While I am not sure, I think that this test is flawed: Windows Vista/7 include an aggressive prefetch service that will populate itself with commonly accessed "HD tracks".
Defragmenting the disk can led to the invalidation of these prefetched tracks, and so boot time will increase. The only...
I run Starcraft 1 on a P3-500 machine w/128 MB RAM with no problem on large 4x4 maps, so it is not a CPU problem, really.
With OS are you using? The graphic card driver are correctly installed? Sorry for the very "dumb" questions, but it is very strange that you have problem with an Opteron...
Yeah, I agree.
Moreover, enterprise servers often have RAID controller with aboundant DRAM cache that is used for this very same purpose: limit the number of total I/O operations passed to the disk (or SSD) backend.
So I see this ReRAM cache as a mean to drive cost low, rather then to...
Hi,
WD Green series reliability tend to suffer due to too much aggressive head parking behaviour. As the head attuator should last a large, but finite number of times (~100.000) in some circumstance the drive can break due to head attuator wearing.
This is rarely a problem with desktop...
Correct.
Defragmenting an SSD means to do a lot of writes on it, while performance will be identical. For this very reason, if Windows7 see a SSD it automatically disable the build-in defragmenter.
Regards.
I understand that Intel can be a fierce competitor, but it seems to me that IB is the first acceptable IGP from them. SB, albeit decent from a performance standpoint, has terrible IQ.
I think that for another 1 or 2 IGP generations, AMD will be faster. However, they risk to see their speed...
Interesting. I should try with my Arrandale-based notebook...
Yes, this was needed to prevent the OS to too often assign two threads to a single module. The downside is reduced Turbo-core efficiency and increased power consumption. And the results speak for themselves: with this patch...
I don't think that the small L1 cache is a direct consequence of saving die space: L1 cache wil remain very small (from a die estate point) at 32 or 64 KB also.
I think that the small L1 and the relatively low associativity are due to the high planned clock speed to be reached. The real problem...
Based on Anandtech data (http://www.anandtech.com/show/5057/the-bulldozer-aftermath-delving-even-deeper/10) it seems that L1, while small, has decent hit rates.
Surely increase it 2X would be useful, but I think the real culprit is the write-through approach, coupled with the very small WCC...
This is true, but modern operating systems tend to don't move threads between cores without a very good reason: http://www.tomshardware.com/reviews/intel-core-i5,2410-8.html
With Windows Vista it was a major concern for AMD Phenom CPU, as you correcly noted.
A Bulldozer-specific problem that...
Yes, you are right: after further research, I found an Intel article claiming that GMA X3000 and up don't use zone rendering. Interesting find ;)
Something can be done (see later)...
This make a lot of sense, I must say... :)
I often found these kind of accelerator called "hybrid" or...
I see your point here: I was not thinking to the needed storage buffer for very complex tiles. Maybe true TBR accelerator will remain a PowerVR affair... :whiste:
The linked PDF refers to i915g chipset with Intel GMA900, not on GMA500 (licensed by PowerVR) and used on Poulsbo and similar...
Triangle list generation can be accelerated by special hardware. I think this was the case with some Naomi arcade, but I can go wrong.
Anyway, with no new DRAM standard in the near term (DDR4 has a long way) and no eDRAM, I think that, if AMD want to significantly increase its graphic...
If bandwidth will become an insurmountable problem, I think AMD can push a more tile-based approach to somewhat work around bandwidth limitation.
Intel use a partial zone-rendering approach in their chipset/GMA, but true tile-rendering is very hard to do without artifact.
So, due to its...
Yes, bronxzv already posted me the realworldtech thread were this was discussed ;)
What I means is that, in the linked PDF, Intel itself consider non-destructive instructions a "key feature", so I wonder if it is really useful for some.
Thank you for your clarifications. :)
One more thing: I don't think that AMD will use an embedded cache/memory for graphics in the near/medium terms. AMD (as Nvidia) has an immense knowledge of graphics workload, so I think that they can improve performance without a such expensive (from a die space standpoint) strategy.
Intel, on...
As stated above, textures don't require huge caches: when a group of pixels is being rendered, the required texture space is often in the range of only some kilobyte.
As an example, see the R600 vs RV770 case: the first used a relatively large, shared texture cache, while the latter use a...
While it will be exciting, I think that we will never see anything similar on a CPU: an high programmable DSP will be similar to a CPU with large amount of dedicated fixed logic, eating into programmable one (cores) and interconnects. Fixed function logic is great, but only with a relatively...
Great paper, thank you.
As a note: in this document, Intel claimed non-destructive operations as a new "key feature" of AVX instructions. Maybe non-destructive semantic can be useful in some case (apart the simplified assembly code generation)?
Thanks.
I can see your point (fixed hardware in the days where anything is programmable) but I really think that Quicksync-like features have their reasons.
Fixed hardware can be tenfold more efficient that programmable one, obviously with the correct workload. And while our Teraflop, programmable...
Yeah, this is true.
However, the lower end chips generally remain with very few units anyway. Think to the Radeon 2400XT-5450: four different chip generation and three process nodes after, they come from 40 sp / 4 TMU to 80 sp / 8 TMU only (and ROPs remained the same).
It's not a case that the...
Hi,
with IB/Llano/Trinity the lower end cards (AMD 5450 / 6450 and NVIDIA GT 220 / 210) begin to be really questionable already: http://www.anandtech.com/show/4263/amds-radeon-hd-6450-uvd3-meets-htpc/5
To tell the truth, Trinity is more or less equally capable that a Radeon 5570, so the low...
Hi,
the naming confusion between DDR and GDDR is quite annoying.
GDDR3 was based on DDR2 technology, as it used the same 4-bit prefetch. However, GDDR3 included some improvements that helped clock scaling.
GDDR4 are based on DDR3 technology, using 8-bit prefetch. So, on a DDR generational...
As ShintaiDK already wrote, a dedicated L2 cache was needed because sharing the L2 cache between 4 cores will be slow.
So, with Nehalem Intel went the reverse route: it create a small, very fast L2 cached backed by a slower and bigger L3 cache.
This inclusive L3 cache permits:
- fast data...
My worse CPU was a P4-Celeron w/128 L2 cache @ 2.0 GHz.
The P4 uarch, means that any workload exceeding L2 cache is going to be very slow, and with only 128 KB L2 cache many workloads are slow on this kind of celeron.
For example, with many website that make decent/heavy use of...
It sound a little strange to me that Haswell-EP will have 16 cores.
I expect the 16 core version to be relegated to Haswell-EX market, not to the lower EP.
Well, time will tell.
Regards.
The thermal paste was correctly applied on these processors: the gold rectangle that you see is the IHS for the 2 dies componing a PPro.
However, the ceramic substrate was really smashed: considering that it is quite hard, these processors were kept very badly!
Regards.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.