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    Russian woman charged with spying for Moscow by 'infiltrating' NRA

    "The Russophobic witch hunt has its first real life victim in 29 year old Maria Butina, whose life is to be destroyed for chatting up members of the NRA in order to increase Russian influence. With over 20 years of diplomatic experience, I can tell you that every country, including the UK and...
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    AMD Ryzen (Summit Ridge) Benchmarks Thread (use new thread)

    Urs Hölzle is Senior Vice President for Technical Infrastructure at Google: https://www.nextplatform.com/2015/04/29/google-will-do-anything-to-beat-moores-law/ Considering that hyperscalers (Amazon, Facebook, Google, etc...) control their own software stacks from the operating system kernel...
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    Samsung/GloFo EUV 7nm node: gate pitch and interconnect pitch

    GatePitch x FinPitch = Transistor Area GatePitch x MetalPitch determine cell area. The problem with that forecast is that Intel's N10 manufacturing process area scaling is not achieved using dimensional scaling only. Have you ever asked yourself why Intel stopped using the simple GatePitch x...
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    TSMC 7nm info

    Historically, scaling the metal interconnect has been the most challenging aspect of a node shrink. Yes, the metal pitch size tells a lot not only about logic density but also about the difficulty of the node. Furthermore, the fin pitch is tied to the choice of metal pitch to provide enough fin...
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    TSMC 7nm info

    Is this for SRAM density, logic density, or both? SRAM density is mainly determined by CGP (Contacted Gate Pitch) in one direction and isolation pitch in the other direction. MP (Metal Pitch) is usually not a limiting factor because an SRAM column only needs four metal lines: Vdd, Vss, BL, and...
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    TSMC 7nm info

    Most people appear to have missed the most important piece of information in GF's N7 technology announcement: http://www.eetimes.com/document.asp?doc_id=1330467&page_number=2 You can easily infer two things from this: First, they are moving to 1D design levels because mapping 2D design...
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    Why didn't Apple have Intel manufacture their chips?

    double post sorry!
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    Why didn't Apple have Intel manufacture their chips?

    - Transition from x86 to ARM. - Pit Intel Custom Foundry against TSMC for manufacturing the chips. - Lower the price of Macs to reduce the Mac tax and use iOS to make inroads into the Enterprise market which has the potential to be huge.
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    New Zen microarchitecture details

    First, the author of the article made several mistakes including die shrink, and has already updated his story. Second, in order for that observation of the "analysts" to be true, Intel's N10 process technology should deliver a gate pitch about 45nm and a metal pitch about 30nm. Both pitches of...
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    ARM and Intel team up for 10nm

    The half-pitch (HP) is defined by the Rayleigh Resolution Equation. The smallest HP that can be printed in single exposure is 36 nm. However, a k1 process factor of 0.25 is considered to be a very difficult, if not impossible, process. Today's best processes have k1 = 0.28. So, the practical...
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    ARM and Intel team up for 10nm

    The smallest feature that can be printed with self-aligned double patterning (SADP) is 40nm. A metal pitch size of 32-34nm would require self-aligned quadruple patterning (SAQP) or EUV. The area scaling of 0.46x appears to be achieved using both dimensional (feature size) and functional...
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    ARM and Intel team up for 10nm

    It seems ground rules for N10 processes will look as follows: Intel N10 process: Fin Pitch: 32nm Gate Pitch: 54nm Metal Pitch: 42nm (1D layout) Samsung N10 process: Fin Pitch: 42nm Gate Pitch: 64nm Metal Pitch: 48nm (2D layout) TSMC N10 process: Fin Pitch: 34nm Gate Pitch: 64nm Metal Pitch...
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    New Zen microarchitecture details

    POWER6 was a high-frequency IN-ORDER micro-architecture with a short 13-FO4 pipeline structure.
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    Intel microarchitecture: Nehalem v. Skylake

    In terms of superscalar hardware data structures, Nehalem was a Data-in-ROB (ReOrder Buffer) design, whereas Sandy Bridge (re)introduced the Unified-PRF (Physical Register File) design. - Data-in-ROB: P6 up to Nehalem and Westmere - Unified-PRF: P4, Sandy Bridge up to Skylake...
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    Intel Investor Meeting 2015: November 19

    Intel N22: Gate Pitch: 90nm Metal1: 90nm Metal2: 80nm 1D layouts Samsung N20: Gate Pitch: 90nm Metal1: 80nm Metal2: 80nm 2D layouts You are suggesting that 1D layouts are density neutral. Do you have any source on this? Thanks. PS: The numbers are from Dick James, Chipworks...
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    Intel Investor Meeting 2015: November 19

    Higher performance transistors built with III-V materials is one of the smaller pieces of the problem. Even though they would most probably require different materials, co-integration of nFET and pFET is also relatively easy compared to real challenge. The real challenge is how to process these...
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    [Techpowerup] AMD "Zen" CPU Prototypes Tested, "Meet all Expectations"

    Taller gates allow larger transistor widths to be used, equating to higher performance: Ultra High Density: 7 or 8-track High Density: 9 or 10-track High Performance: 12-track OTOH, when designers compare their 12-track library at N28 (planar bulk) to their N16/N14 (FinFET bulk) 9-track...
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    Apple A9X the new mobile SoC king

    I provided a link to the article because the battle methaphor is from Morris Chang himself: I know some people on first term basis who ported their N28 planar bulk libraries to the TSMC N16 FinFET flow. So, I have some idea as to why TSMC N16 FinFET is in its second generation. The following...
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    Apple A9X the new mobile SoC king

    "Lies, damned lies, and statistics". Apparently, TSMC lost the N16 battle in 2014. http://semiengineering.com/whos-winning-the-finfet-foundry-race/
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    Intel Skylake / Kaby Lake

    From Page 6 Sidebar: http://www-inst.eecs.berkeley.edu/~ee130/sp06/chp7full.pdf
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    Intel Q2 Financials- revenue down, profit down, datacenter up

    You seem to be using node names for making some calculations. There is nothing on the 22nm node that measures 22nm, and nothing on 14nm node that measures 14nm unless by a coincidence. According to Intel, 14nm SRAM memory cell scaled 0.54x whereas the logic area scaled 0.53x.
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    [DigiTimes] TSMC 10 nm trial production in 2015, mass production in 2016

    A node with a 1Xnm HP (Half Pitch) has different EUV mask requirements than a node with 2Xnm HP. According to Intel and Toshiba, there are significant infrastructure gabs for 1Xnm HP EUV mask. The Intel 10nm node logic design rules will somewhat be more similar to 1Xnm memory design rules...
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    Intel Cannonlake 10 nm delayed, introducing KabyLake

    GlobalFoundries and Samsung are GDSII compatible. So, It is possible to use a single PDK to carry out a single design, and send a single GDSII file to either company. They are not, however, mask compatible: http://semimd.com/blog/2014/04/17/globalfoundries-and-samsung-join-forces-on-14nm-finfets/
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    Fudzilla: New AMD Zen APU boasts up to 16 cores (plus Greenland GPU with HBM)

    I don't think fixed cost or investment is in that slide. However, cost seems to be a sensitive issue so they are using # of litho steps as well as # OVL (overlay) metrology in recent slides:
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    Fudzilla: New AMD Zen APU boasts up to 16 cores (plus Greenland GPU with HBM)

    So, if they save money by running 10nm wafers through 50% faster, why not do this for 14nm as well? Oh, because then it would become apparent that 10nm is more expensive. The cost of multiple patterning techniques according to ASML:
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    Fudzilla: New AMD Zen APU boasts up to 16 cores (plus Greenland GPU with HBM)

    The costs are going up because of multiple patterning. Lars Liebmann at IBM has a cost chart for the various techniques: The foundries are using LELE (Litho-Etch-Litho-Etch) whereas Intel is using SADP (Self Aligned Double Patterning). Compared to SE (Single Exposure), LELE is 2.5x and...
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    TSMC 10nm details (TSMC Symposium)

    Hans, Is it not the completely free form 2D metal layers community finding it difficult to go forward unless they can insert EUV? In order to deliver dense cell libraries, the metal layers (the first metal, in particular) have to be 2D or multidirectional. However, triple patterning technology...
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    TSMC 10nm details (TSMC Symposium)

    For what it's worth, there are different ways of normalizing the drive current of FinFET devices. You could report 20% - 30% higher drive currents playing normalization tricks. However, some device engineers consider that cheating and put footnotes to their papers. Jan et al [14] is Intel...
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    Intel 10nm delayed by 9 months? (Semiengineering)

    Thanks, but I am trying to understand the basis of "maybe TSMC 10nm will still be like Intel 14nm in density." How will "TSMC 10nm will still be like Intel 14nm in densiy?" Thanks again.
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    Intel 10nm delayed by 9 months? (Semiengineering)

    How do you benchmark a process? Thanks.
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    Samsung Exynos Thread (big.LITTLE Octa-core)

    ChipWorks has probably already given a bevel polish to the die so that they can look at the transistors in plan view. Presumably, they will share TEM images from their analysis report showing the fin pitches, number of metal layers, interconnect pitch etc.
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    Samsung Exynos Thread (big.LITTLE Octa-core)

    The pitch of Intel 22nm process metal one is 90nm whereas metal two is 80nm - presumably to optimize pin access into standard cells. The first-level metal is instrumental for intra-cell routing because it can freely traverse layout items on any other conducting layer, can connect to all...
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    I'm confused about Intels 14nm process lead

    I should let Hans answer this, but I believe his basic argument is that Intel has a density disadvantage because it is using 1D routing. Transistor counts follow from his 1D vs 2D routing argument. He even asked whether Intel would go back to 2D routing. I do not think Intel would even consider...
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    I'm confused about Intels 14nm process lead

    Well come to the bottom! As Richard Feynman said: "There's Plenty of Room at the Bottom." I can tell stories about how Intel normalizes its drive currents, and you can tell your stories about 1D metals vs 2D metals. When, if at all, Intel discloses the transistor count and the die size...
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    I'm confused about Intels 14nm process lead

    I believe they intend to use 2D routing on metal 1, and 1D routing at the layers above metal 1. They also intend to use SADP to deliver 40nm metal pitches, and as far as I know SADP is 1D. So, the big unknown appears to be how TSMC will map the 40nm 2D metal 1 onto SADP. I have seen some...
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    I'm confused about Intels 14nm process lead

    Intel claims that 1D metals are density neutral or have better density than 2D metals. However, there are other semiconductor companies who say that 1D metals have a die cost. Again, silicon does not lie. And, silicon data so far failed to support the original 35% better density claim. I...
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    I'm confused about Intels 14nm process lead

    I have actually read up on the difference between 1D and 2D layouts. 1D metals have several advantages over 2D metals. For example, air gabs in the copper interconnects for logic require regularly spaced 1D line arrays as a design constraint. However, I find it hard to believe that 1D metals are...
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    I'm confused about Intels 14nm process lead

    As far as the apparent density advantage of Apple A8 is concerned, they appear to have conveniently chosen to keep mum about the die cost of 1D metals.
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    I'm confused about Intels 14nm process lead

    Using the metal 3 pitch (if you start counting from 1) in the Gate Pitch x Metal Pitch heuristic is a nice metal 1 marketing trick from Intel. Furthermore, the Gate Pitch x Metal Pitch heuristic conveniently ignores the die cost of 1D metals. Be that as it may, silicon does not lie. And the...
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    I'm confused about Intels 14nm process lead

    That figure is from an excellent article from Hiroshige Goto about the complexity of routing with finFETs. http://pc.watch.impress.co.jp/docs/column/kaigai/20141014_671062.html When he wrote that article Intel had not disclosed the pithes of its lowest metal layers yet. As such, it was not...
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