During yesterday's fierceful fight I found indications that the Borg do
have feelings. They seem to a enjoy a good spanking every now and then ;)
Cpt. Riv
Argh, I inadvertently fired a tachyon burst when I was supposed to just power up my shields :o Maybe I should install a by-pass mechanism to prevent this from happening again.
Cpt. Riv
Just noticed a new client has been released for Win32. From changes.txt:
2.8012.465 fix: all: -n -1 (exit on empty buffers) works again.
fix: win32: restore from tray works again
fix: win16: text appearing as a single line fixed
new: win32: rate and in-buffer...
That's interesting. Sometimes my cursor moves a little in Win2k without the mouse being moved. I can't see how that can be related to the Dnet client though.
DanC,
That seems strange. I've been using Win2k since it came out and I'm doing what the TA distributed computing speeds chart says I should (on a P3 500 running at 100MHz bus). Hit Ctrl+Alt+Del and check the task manager to see if there are any performance killers running. Also run the Dnet...
Your DNet ID is not used for accessing your profile on TA's site. Look through your old e-mails and see if you can find one from admin@teamanandtech.com containing your login and password.
Excellent job all authors! OGR certainly sounded a lot more interesting :) If I wasn't already participating in many of TA's projects I'd join!
PS. I also agree with xrayman.
There were a few integer instructions introduced with SSE, but they only operated on 64-bit (the MMX) registers. SSE2 brings 128-bit SIMD integer instructions.
I was wondering if anybody has a list of professional applications known to run idle priority threads. I'm mainly interested in knowing what applications would often/always run such threads.
I know that Celeron and P2/P3 processors have been experiencing 10-15% speedups. If AMD K6 processors are slower, well, not much to do about it (simply use the best client). In the latest released source (from May I think) the OGR code was all ANSI C so there were no processor specific cores and...
If Intel tries to write a P4 RC5 core I hope they realize the usefulness of a SIMD rotate instruction- especially if each partial register could be rotated a different amount than the others (e.g. rotate the high 32 bits 4 steps to the left and rotate the low 32 bits 7 steps to the left) =)
Hmm, last time I checked the dnet client source there were no special P3 core at all, just the PPro class core. That core don't even use MMX (but the P5 MMX core sucks at P3 anyway...) For quickly start coding SSE2 the P4 instruction set reference manual and the basic architecture manual should...
Welcome aboard Reaper! If you haven't already you should pay the Team AnandTech Website a visit. I highly recommend the tutorials, signing up as a member and signing up to receive the newsletter.
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:Q I'm from the Federated States of Micronesia can't you read :) I thought it was hilarious that I could choose a state even though they only apply to the US. Hmm, wonder how many weird glyphs turns up now :cool:
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