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What controls Turbo Core in Xeons?

If you have one of the cpuid=0x306f2 QFxx C0-step CPUs, congratulations, your chip runs faster than the official ones, although I wouldn't run PCIe gen3 on them! If, on the other hand, you have a cpuid=0x306f1 B-step CPU, you'll probably not be able to apply this hack as the chips usually need...
- evilr00t
- Post #2,128
- Jan 2, 2018
- Forum: CPUs and Overclocking
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What controls Turbo Core in Xeons?

if you're using an ES1 chip that uses microcodes with a mask of 0x80000000, you almost certainly won't find it in the cpumcupdate dll unless you add it yourself. That should be able to be extracted from your BIOS if it has a 0x80000000 mc update, which it almost certainly does.
- evilr00t
- Post #1,915
- Nov 23, 2017
- Forum: CPUs and Overclocking
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Working SD card RESISTING 10+ ways of FORMAT

Your SD card is toast, and becoming read-only/write-resistant is the Right Way for a solid state drive to fail. RMA it if there isn't anything valuable/sensitive on it, hammer it otherwise.
- evilr00t
- Post #8
- Nov 17, 2017
- Forum: Memory and Storage
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What controls Turbo Core in Xeons?

I have no doubt the hack works on earlier chips, however, there are many caveats to working with early engineering samples. ES0 (306f0) chips are garbage, turn them into keychains. I've never managed to get one to boot into Windows. I wouldn't expect any shipping BIOS to keep microcodes for this...
- evilr00t
- Post #1,730
- Oct 19, 2017
- Forum: CPUs and Overclocking
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Dual XEON 2696 v4 + Supermicro X10DAX Build - BSOD frequently - please help

9812 - nvidia driver bug The rest: whea uncorrectable. 0xf200020000010005 - Proc 67, bank 0 - 14265 0xb200000000010005 - Proc 66, bank 0 - 14250 0xf2001b8000010005 - Proc 66, bank 0 - 14078 0xf200d88000010005 - Proc 66, bank 0 - 10765 Bank 0 is the CPU L1 instruction cache. Notice how all of...
- evilr00t
- Post #7
- Oct 14, 2017
- Forum: CPUs and Overclocking
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Dual XEON 2696 v4 + Supermicro X10DAX Build - BSOD frequently - please help

The last xeons to need mismatched stepping support were the Sandy Bridge Xeons, so if your cpuid's don't match, you're running an ES with a retail stepping of the chip. That's unsupported and will blow up. whea uncorrectable error bad hardware - post your crash dump (you should have a minidump...
- evilr00t
- Post #5
- Oct 13, 2017
- Forum: CPUs and Overclocking
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CPU for Floats crunching

That's interesting as hell. Is Bristol Ridge the first consumer GCN implementation to do 1 : 2 SP : DP?
- evilr00t
- Post #28
- Sep 16, 2017
- Forum: CPUs and Overclocking
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CPU for Floats crunching

I'd love to see these reports myself. IIRC GCN3 (Tonga/Fiji) had 1:16 SP:FP ratio. The A12's IGP has about 1.1 SP TFLOPS, I'd be surprised to see 500 DP GFLOPS out of it.
- evilr00t
- Post #24
- Sep 16, 2017
- Forum: CPUs and Overclocking
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Vega refresh - Expected? How might it look?

There seems to be a lot of FUD around nVidia's equivalent to AMD's HBCC (iommu, copy engine, virtual addressing, paging). The IOMMU and copy engine have been around since before Kepler (unified memory). *see edit below What's new in Pascal is "49-bit virtual addressing and on-demand page...
- evilr00t
- Post #139
- Aug 31, 2017
- Forum: Graphics Cards
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AMD Radeon RX Vega 64 and 56 Reviews [*UPDATED* Aug 28]

I have a hard time believing this. A simple OpenCL program to allocate 6GB of device memory (and read through it sequentially periodically, to see the impact of HBCC page migration) should have the same impact as restricting VRAM to 2GB.
- evilr00t
- Post #1,272
- Aug 28, 2017
- Forum: Graphics Cards
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Vega refresh - Expected? How might it look?

This seems to be a Pascal (CC6.0+) feature, and doesn't seem restricted to GP100. Citation needed on paging granularity, and why this matters. Here's a dump of a modified deviceQuery on my GP107 card: Device 2: "GeForce GTX 1050 Ti" CUDA Driver Version / Runtime Version 8.0 / 8.0...
- evilr00t
- Post #95
- Aug 27, 2017
- Forum: Graphics Cards
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What controls Turbo Core in Xeons?

I think the QS0/C0 chips have higher turbo multipliers.
- evilr00t
- Post #1,413
- Aug 27, 2017
- Forum: CPUs and Overclocking
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What controls Turbo Core in Xeons?

Dual CPU boards usually route PCIe lanes out from each cpu, so depending on the number of Wellsburg chips, could be 40 (CPU Integrated IO) + 8 (Wellsburg PCH) per CPU. Typically you only see one Wellsburg [edit: per board, not per CPU] though - multi-PCH setups are very unusual even in the...
- evilr00t
- Post #1,324
- Aug 13, 2017
- Forum: CPUs and Overclocking
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Good SATA port add-in card?

I would be _really_ careful with any Marvell SATA controller with drives over 2.2TB (3TB+). I've encountered silent data corruption, where occasionally, if writing to an address above 2TB, it'll subtract 2TB and write to that address instead; I'm glad I had btrfs to tell me that corruption had...
- evilr00t
- Post #3
- Aug 9, 2017
- Forum: Memory and Storage
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What controls Turbo Core in Xeons?

If I'm interpreting this correctly, the bootstrap processor is usually CPU0, so I'd put the newer (retail) chip there. It probably doesn't matter because both are QS-C1 chips (the retail version just has the ES flag unset).
- evilr00t
- Post #1,292
- Aug 8, 2017
- Forum: CPUs and Overclocking
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What controls Turbo Core in Xeons?

QGNx is C1 QS, which is also the retail stepping. Generally speaking, mixing steppings in multi-cpu configurations is supported by Intel, as long as the stepping difference isn't greater than one. The UEFI is responsible for downgrading the features to the oldest stepping. The last time this...
- evilr00t
- Post #1,290
- Aug 8, 2017
- Forum: CPUs and Overclocking
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Haswell E De-Lidded

That early engineering sample chip might have four dark cores, but final silicon will have 8 cores natively. The low end chips usually get taped out later, so Intel makes chop versions of higher end chips so developers can work on them.
- evilr00t
- Post #38
- Aug 1, 2014
- Forum: CPUs and Overclocking
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Intel Xeon E5 v3 (Haswell-EP) will be available with up to 18 cores (45MB L3)

Not necessarily - in the case of two CPUs in separate sockets, you can use more memory channels (4 per chip, instead of 2 per chip in the single-chip dual-die hypothetical). As applied to the real world where 1x12c vs. 2x6c, I'd have to change the line in my previous post about why you pick 2...
- evilr00t
- Post #20
- Jul 31, 2014
- Forum: CPUs and Overclocking
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Intel Xeon E5 v3 (Haswell-EP) will be available with up to 18 cores (45MB L3)

The two die solution connected via QPI could be considered a sort of dual-processing on one chip. This is always slower than having the cores on die, especially with coherency traffic going over the relatively slow QPI bus (instead of the internal processor ring bus). While it's true the Ivy...
- evilr00t
- Post #18
- Jul 31, 2014
- Forum: CPUs and Overclocking
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Intel Xeon E5 v3 (Haswell-EP) will be available with up to 18 cores (45MB L3)

I don't think VR-zone is necessarily trustworthy or not... It's more likely that Intel didn't want to release 18-core EP chips, so the slide deck presented earlier has them saying it'll only go to 14 cores on EP. Which is why we have the PCN adding the 16 and 18 core variants. On the other...
- evilr00t
- Post #16
- Jul 30, 2014
- Forum: CPUs and Overclocking
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Intel Xeon E5 v3 (Haswell-EP) will be available with up to 18 cores (45MB L3)

Uh, no. The flavors are 8, 12, and 18. See this thread for a 12c chip delid.
- evilr00t
- Post #10
- Jul 30, 2014
- Forum: CPUs and Overclocking
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Haswell E De-Lidded

Looks real, but very lucky to break the chip this way. That's the CPU die stuck to the top of the heat spreader (and the balls under the die not coming up with it - that's been my experience) Considering Haswell-E is going to be a native 8-core die, it's probably one of the early ES chips where...
- evilr00t
- Post #33
- Jul 29, 2014
- Forum: CPUs and Overclocking
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Why does Intel care less about power-saving on the desktop than mobile?

The Ivy chips do run at 800MHz, but you'll have to use software like ThrottleStop to get there. I think this is the MAX_EFFICIENCY_RATIO setting in the CPU MSRs, which is set to x16 on the Desktop SKUs and x12 on the mobile SKUs (at least, this is what my 3740QM does). This doesn't change the...
- evilr00t
- Post #31
- Jun 25, 2014
- Forum: CPUs and Overclocking
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Any Z97 motherboards with 2x PCI x8 and 1x PCI x4 running at the same time

Here's some interesting info for the Haswell consumer/desktop platform: The CPU itself only has 16 lanes of PCIe gen3. This can be bifurcated into: x16 x8+x8 x8+x4+x4 The PCH has 8 lanes of PCIe gen2. This is linked to the CPU via DMI (~x4 Gen2 speed). These are divided into two "bifurcation...
- evilr00t
- Post #9
- Jun 5, 2014
- Forum: Motherboards
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Is a Xeon good for gaming?

1.25x100 yes 1650 and 1660 IVB-E/SNB-E have unlocked bclk mult, not sure about ivy bridge ep (maybe 1680v2 is locked). all chips with qpi are bclk multiplier locked though, I think
- evilr00t
- Post #30
- Nov 14, 2013
- Forum: CPUs and Overclocking
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Haswell IGP chipsets - Does the HD4xxx number effect Quick Sync performance?

set priority to "background" or "idle", problem solved
- evilr00t
- Post #10
- Nov 14, 2013
- Forum: CPUs and Overclocking
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Can I use this RAM in a normal PC?

buffered == registered also buffered memory is usually faster than unbuffered memory in servers where udimm's memory loading causes the max speed to be reduced, see anandtech's server memory article
- evilr00t
- Post #7
- Nov 5, 2013
- Forum: Memory and Storage
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Can I use this RAM in a normal PC?

you can use ecc ram in consumer systems but it won't do anything - unbuffered ecc ram exists but it isn't this one. what you can't do is use REGISTERED ram in consumer systems.
- evilr00t
- Post #4
- Nov 5, 2013
- Forum: Memory and Storage
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Building a Server...Again

The Core i3 also supports ecc if you don't want to spring for a xeon, but it does lack vt-d. Keep that in mind
- evilr00t
- Post #32
- Nov 5, 2013
- Forum: Computer Building

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