This can't be right. There's only 1 compute die in Sierra Forest-SP.
https://wccftech.com/intel-future-xeon-granite-rapids-sp-granite-rapids-ap-sierra-forest-cpus-for-birch-stream-platform-detailed/
*Intel's 10nm was equivalent to foundries' 7nm
*Similarly, Intel's 7nm (renamed to Intel 4/3) is equivalent to something between foundries' 5nm and 3nm
*Intel's 20/18A is a rename from 5nm and is equivelent to foundries' 2nm (remember that Intel does bigger jumps per node, so two Intel nodes may...
Intel already gave their PC TAM update in October, and the PC roadmap (Meteor Lake, Arrow Lake) for 2023-2024 was disclosed at both Investor Meeting and HotChips.
Of course, Intel hasn't announced Raptor Lake Refresh yet, but if there were material delays Intel certainly wouldn't announce such...
This AnandTech slide is an utter misrepresentation of what Intel actually announced in mid-2021. TLDR: Intel's roadmap has remained the same sind mid-2020, there have been 0 delays and 1 pull-in.
*The HVM window for all nodes has always been 6 months. For Intel 4 it was H2'22... And Intel just...
The Intel SDS has been hugely overblown. This is how it has always worked: chip companies create artificial segmentation by artificially disabling features/cores/cache/... in a chip and then charging different amounts for those different SKUs.
The thing that Intel has now realized is that this...
So much FUD...
(1) Alder Lake has longer battery life than Tiger Lake (see the Framework laptop)
(2) Infinity Fabric is the epitome of an overhyped interconnect, it uses over twice as much power (2pJ/bit) as Intel's "decade old" MCM interconnect (1pJ/bit)
(3) People are way too simplistic in...
https://asia.nikkei.com/Business/Tech/Semiconductors/Apple-and-Intel-become-first-to-adopt-TSMC-s-latest-chip-tech
You've been warned before yet i'll inform you once again. You must include your own personal commentary when dropping links or other members quotes.
Daveybrat
AT Moderator
People like @uzzi38 who subscribe to the "Meteor Lake GPU was always 5nm" forget that besides the N3 slide at Investor Meeting, there have been rumors, from multiple sources, that Intel would be first in line for N3 (H2'22 production) as far back as 2020.
Those rumors were confirmed again in...
There were many of these rumors in 2021: https://researchsnipers.com/intel-and-apple-becomes-first-tsmc-customers-for-3nm-process-chip/ https://wccftech.com/intel-to-finalize-3nm-deal-with-tsmc-this-month-as-pilot-production-kicks-off-report/
That's a gross misrepresentation of what I actually said. My previous post contained only facts:
*TSMC announced N3 in 2020 for H2'22 HVM
*However, in 2021 during a Q&A TSMC more precisely specified its schedule as Q3'22
*This has since shifted to (late) Q4'22
Hence, the statement that TSMC is...
Let's directly refer to what TSMC said:
Since N5 entered HVM in April 2020, the statement directly, unambiguously implies that TSMC intended to put N3 in HVM in July-August 2022. However, since TSMC is only expecting N3 revenue in Q1'23, this has been further postponed to (late) Q4 2022. This...
Sounds BS. It comes across as "Intel is incompetent Intel suxx". Lakefield was the world's first (and still only) 3D packaged logic stacking product in the world. Ponte Vecchio is only extending Intel's advanced packaging leadership, and Meteor Lake will widen the gap even more. Ponte Vecchio...
RE: Intel 4/3 transistor density discussion
The goal of this post is to find out what density Intel 3 could achieve.
[TLDR]
Although at first sight I, too, was disappointed by Intel 4, more careful analysis has shown that Intel should readily be able to achieve its 2x density target for Intel...
Emphasis on "if true". Pat Gelsinger went big on saying that the revised Intel 4 uses a ton more EUV than pre-delay. Certainly most important layers (~13 IIRC) are EUV in order to achieve process simplification:
Intel's (stylistic) block diagram from HotChips doesn't show any significant space for EMIB. The whole point of EMIB is that it is a small piece of silicon embedded in the package; it is not part of the main die itself. Those are 10 separate tiles.
Meteor Lake bottom die being just a passive interposer? I don't even.
Meteor Lake is Lakefield 2.0. The bottom die is the PCH, which per tradition is built on the N-1 node, in this case 10nm Foveros.
Proof: see the high density package and tell me where the PCH is...
I'll just leave a few remarks...
-I think it was readily discussed a while ago already that your 82% number is grossly exaggerated
-Intel was on a 1-year cadence with Tick-Tock
-Intel is again on a 1-year cadence since delays solved: Palm, Sunny, Willow, Golden, Ocean Cove, etc. Atom is on a...
https://seekingalpha.com/article/4335290-intel-work-from-home-means-people-need-pcs-and-data-centers-banner-year-ahead
Rules of this forum is to not just drop links. You must comment on what you are linking to.
esquared
Anandtech Forum Director
One Year at Tom’s: Highlights
My Tom’s and “journalist” "career" didn’t start off how I expected: I thought I’d write about Intel, but my first assignment was about Samsung Flashbolt memory. I diligently did some background reading, wrote it, and then it got pubbed… Shortly after, I got my...
The presentation that contained the Tweakers Rocket Lake roadmap dates from ~Jan/Feb'19. The roadmap itself could even be from 2018. So they likely did not start in 2019.
Slide 24 sir.
https://s21.q4cdn.com/600692695/files/doc_financials/2019/Q1/03.30.2019-10Q-Document_FINAL-FILED.pdf
Commentary: "we intend to qualify the 10-nanometer part in the second quarter. So what that means is in the first quarter, all of our 10-nanometer cost is flowing through cost of...
Note: I know the title is similar to a recent article by AnandTech, and due to some recent feedback, I should mention that the content is markedly different, though. Read the AnandTech article if you want just info about 2019's CPUs. I know 2020 already started, but might still be of some...
Uhm. Intel did this because the tech community asked it, was tired of 3-4 yrs of Skylake.
Lakefield is coming this year or early next year, so a year at most.
Remember the difference between announcement and production of 10nm? Silicon photonics? 3DXPoint? 3D NAND? Discrete GPU?
This is...
I created this topic as a general packaging topic, but I will kick things of with EMIB.
Discussion
So I just had a discussion with Ian Cutress on Twitter, but things got heated up a bit lol. So just like EMIB removes the reticle size constraints, I hope this threads removes the character size...
I think after Comet Lake, the 2019 part, Intel is all in on 10nm and will ramp all the 10nm IP as fast as possible imo.
I mean, they should really be in a hurry given TSMC has already 7nm up and running, so I can't imagine them wanting to waste any more time stuck on 14nm and want to move on...
Today, news came in that Ken Addison joins Ryan Shrout from PC Perspective to Intel. As this is the latest notable hire in a series of high-profile hires, I thought it would be interesting to list them up.
(VP = Vice President)
Intel hires overview
Brian Krzanich was quite a polarizing CEO...
Well, if you look before 14nm, Intel had a very good track record. You don't expect to suddenly have a manufacturing catastrophe that causes a three year delay, don't you? You can try to plan ahead for any issues, but something as what happened with 10nm is certainly not something anyone could...
AMD wouldn't have gone bankrupt if 10nm hadn't been delayed, so still don't see your point. Even Tesla which barely has had any profitable quarter ever is still in business. For this exact reason (Intel doesn't even want a monopoly - so competition is also good for Intel to alleviate monopoly...
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